prev_cmp_ctime.tan.qmsg

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 5 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ten:U4\|cout " "Info: Detected ripple clock \"ten:U4\|cout\" as buffer" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ten:U4\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "six:U3\|cou " "Info: Detected ripple clock \"six:U3\|cou\" as buffer" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "six:U3\|cou" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ten:U2\|cout " "Info: Detected ripple clock \"ten:U2\|cout\" as buffer" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ten:U2\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "six:U1\|cou " "Info: Detected ripple clock \"six:U1\|cou\" as buffer" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "six:U1\|cou" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ten:U0\|cout " "Info: Detected ripple clock \"ten:U0\|cout\" as buffer" {  } { { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "ten:U0\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "set " "Info: Detected ripple clock \"set\" as buffer" {  } { { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "set" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register six:U5\|b\[2\]\$latch register set 41.47 MHz 24.114 ns Internal " "Info: Clock \"clk\" has Internal fmax of 41.47 MHz between source register \"six:U5\|b\[2\]\$latch\" and destination register \"set\" (period= 24.114 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.983 ns + Longest register register " "Info: + Longest register to register delay is 1.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns six:U5\|b\[2\]\$latch 1 REG LC_X8_Y8_N2 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y8_N2; Fanout = 12; REG Node = 'six:U5\|b\[2\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { six:U5|b[2]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.590 ns) 1.042 ns process0~51 2 COMB LC_X8_Y8_N7 1 " "Info: 2: + IC(0.452 ns) + CELL(0.590 ns) = 1.042 ns; Loc. = LC_X8_Y8_N7; Fanout = 1; COMB Node = 'process0~51'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.042 ns" { six:U5|b[2]$latch process0~51 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.463 ns) + CELL(0.478 ns) 1.983 ns set 3 REG LC_X8_Y8_N1 33 " "Info: 3: + IC(0.463 ns) + CELL(0.478 ns) = 1.983 ns; Loc. = LC_X8_Y8_N1; Fanout = 33; REG Node = 'set'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.941 ns" { process0~51 set } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.068 ns ( 53.86 % ) " "Info: Total cell delay = 1.068 ns ( 53.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.915 ns ( 46.14 % ) " "Info: Total interconnect delay = 0.915 ns ( 46.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.983 ns" { six:U5|b[2]$latch process0~51 set } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.983 ns" { six:U5|b[2]$latch {} process0~51 {} set {} } { 0.000ns 0.452ns 0.463ns } { 0.000ns 0.590ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-10.037 ns - Smallest " "Info: - Smallest clock skew is -10.037 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.164 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.164 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(0.711 ns) 4.164 ns set 2 REG LC_X8_Y8_N1 33 " "Info: 2: + IC(1.984 ns) + CELL(0.711 ns) = 4.164 ns; Loc. = LC_X8_Y8_N1; Fanout = 33; REG Node = 'set'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { clk set } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 52.35 % ) " "Info: Total cell delay = 2.180 ns ( 52.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.984 ns ( 47.65 % ) " "Info: Total interconnect delay = 1.984 ns ( 47.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.164 ns" { clk set } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.164 ns" { clk {} clk~out0 {} set {} } { 0.000ns 0.000ns 1.984ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 14.201 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 14.201 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(0.935 ns) 4.388 ns set 2 REG LC_X8_Y8_N1 33 " "Info: 2: + IC(1.984 ns) + CELL(0.935 ns) = 4.388 ns; Loc. = LC_X8_Y8_N1; Fanout = 33; REG Node = 'set'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.919 ns" { clk set } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.671 ns) + CELL(0.292 ns) 9.351 ns ten:U4\|cout 3 REG LC_X8_Y8_N4 4 " "Info: 3: + IC(4.671 ns) + CELL(0.292 ns) = 9.351 ns; Loc. = LC_X8_Y8_N4; Fanout = 4; REG Node = 'ten:U4\|cout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.963 ns" { set ten:U4|cout } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.558 ns) + CELL(0.292 ns) 14.201 ns six:U5\|b\[2\]\$latch 4 REG LC_X8_Y8_N2 12 " "Info: 4: + IC(4.558 ns) + CELL(0.292 ns) = 14.201 ns; Loc. = LC_X8_Y8_N2; Fanout = 12; REG Node = 'six:U5\|b\[2\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.850 ns" { ten:U4|cout six:U5|b[2]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.988 ns ( 21.04 % ) " "Info: Total cell delay = 2.988 ns ( 21.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.213 ns ( 78.96 % ) " "Info: Total interconnect delay = 11.213 ns ( 78.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.201 ns" { clk set ten:U4|cout six:U5|b[2]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.201 ns" { clk {} clk~out0 {} set {} ten:U4|cout {} six:U5|b[2]$latch {} } { 0.000ns 0.000ns 1.984ns 4.671ns 4.558ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.164 ns" { clk set } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.164 ns" { clk {} clk~out0 {} set {} } { 0.000ns 0.000ns 1.984ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.201 ns" { clk set ten:U4|cout six:U5|b[2]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.201 ns" { clk {} clk~out0 {} set {} ten:U4|cout {} six:U5|b[2]$latch {} } { 0.000ns 0.000ns 1.984ns 4.671ns 4.558ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.292ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.983 ns" { six:U5|b[2]$latch process0~51 set } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.983 ns" { six:U5|b[2]$latch {} process0~51 {} set {} } { 0.000ns 0.452ns 0.463ns } { 0.000ns 0.590ns 0.478ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.164 ns" { clk set } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.164 ns" { clk {} clk~out0 {} set {} } { 0.000ns 0.000ns 1.984ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.201 ns" { clk set ten:U4|cout six:U5|b[2]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.201 ns" { clk {} clk~out0 {} set {} ten:U4|cout {} six:U5|b[2]$latch {} } { 0.000ns 0.000ns 1.984ns 4.671ns 4.558ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.292ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 20 " "Warning: Circuit may not operate. Detected 20 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "set six:U5\|b\[0\]\$latch clk 7.414 ns " "Info: Found hold time violation between source  pin or register \"set\" and destination pin or register \"six:U5\|b\[0\]\$latch\" for clock \"clk\" (Hold time is 7.414 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "10.050 ns + Largest " "Info: + Largest clock skew is 10.050 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 14.214 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 14.214 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(0.935 ns) 4.388 ns set 2 REG LC_X8_Y8_N1 33 " "Info: 2: + IC(1.984 ns) + CELL(0.935 ns) = 4.388 ns; Loc. = LC_X8_Y8_N1; Fanout = 33; REG Node = 'set'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.919 ns" { clk set } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.671 ns) + CELL(0.292 ns) 9.351 ns ten:U4\|cout 3 REG LC_X8_Y8_N4 4 " "Info: 3: + IC(4.671 ns) + CELL(0.292 ns) = 9.351 ns; Loc. = LC_X8_Y8_N4; Fanout = 4; REG Node = 'ten:U4\|cout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.963 ns" { set ten:U4|cout } "NODE_NAME" } } { "ten.vhd" "" { Text "D:/EDA/030501713/time/ten.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.571 ns) + CELL(0.292 ns) 14.214 ns six:U5\|b\[0\]\$latch 4 REG LC_X9_Y8_N3 11 " "Info: 4: + IC(4.571 ns) + CELL(0.292 ns) = 14.214 ns; Loc. = LC_X9_Y8_N3; Fanout = 11; REG Node = 'six:U5\|b\[0\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.863 ns" { ten:U4|cout six:U5|b[0]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.988 ns ( 21.02 % ) " "Info: Total cell delay = 2.988 ns ( 21.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.226 ns ( 78.98 % ) " "Info: Total interconnect delay = 11.226 ns ( 78.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.214 ns" { clk set ten:U4|cout six:U5|b[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.214 ns" { clk {} clk~out0 {} set {} ten:U4|cout {} six:U5|b[0]$latch {} } { 0.000ns 0.000ns 1.984ns 4.671ns 4.571ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.164 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 4.164 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.984 ns) + CELL(0.711 ns) 4.164 ns set 2 REG LC_X8_Y8_N1 33 " "Info: 2: + IC(1.984 ns) + CELL(0.711 ns) = 4.164 ns; Loc. = LC_X8_Y8_N1; Fanout = 33; REG Node = 'set'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { clk set } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 52.35 % ) " "Info: Total cell delay = 2.180 ns ( 52.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.984 ns ( 47.65 % ) " "Info: Total interconnect delay = 1.984 ns ( 47.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.164 ns" { clk set } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.164 ns" { clk {} clk~out0 {} set {} } { 0.000ns 0.000ns 1.984ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.214 ns" { clk set ten:U4|cout six:U5|b[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.214 ns" { clk {} clk~out0 {} set {} ten:U4|cout {} six:U5|b[0]$latch {} } { 0.000ns 0.000ns 1.984ns 4.671ns 4.571ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.292ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.164 ns" { clk set } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.164 ns" { clk {} clk~out0 {} set {} } { 0.000ns 0.000ns 1.984ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.412 ns - Shortest register register " "Info: - Shortest register to register delay is 2.412 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns set 1 REG LC_X8_Y8_N1 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y8_N1; Fanout = 33; REG Node = 'set'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { set } "NODE_NAME" } } { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.271 ns) + CELL(0.292 ns) 1.563 ns six:U5\|b~158 2 COMB LC_X9_Y8_N4 1 " "Info: 2: + IC(1.271 ns) + CELL(0.292 ns) = 1.563 ns; Loc. = LC_X9_Y8_N4; Fanout = 1; COMB Node = 'six:U5\|b~158'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.563 ns" { set six:U5|b~158 } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.442 ns) 2.412 ns six:U5\|b\[0\]\$latch 3 REG LC_X9_Y8_N3 11 " "Info: 3: + IC(0.407 ns) + CELL(0.442 ns) = 2.412 ns; Loc. = LC_X9_Y8_N3; Fanout = 11; REG Node = 'six:U5\|b\[0\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.849 ns" { six:U5|b~158 six:U5|b[0]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.734 ns ( 30.43 % ) " "Info: Total cell delay = 0.734 ns ( 30.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.678 ns ( 69.57 % ) " "Info: Total interconnect delay = 1.678 ns ( 69.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.412 ns" { set six:U5|b~158 six:U5|b[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.412 ns" { set {} six:U5|b~158 {} six:U5|b[0]$latch {} } { 0.000ns 1.271ns 0.407ns } { 0.000ns 0.292ns 0.442ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "ctime.vhd" "" { Text "D:/EDA/030501713/time/ctime.vhd" 23 -1 0 } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.214 ns" { clk set ten:U4|cout six:U5|b[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.214 ns" { clk {} clk~out0 {} set {} ten:U4|cout {} six:U5|b[0]$latch {} } { 0.000ns 0.000ns 1.984ns 4.671ns 4.571ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.292ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.164 ns" { clk set } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.164 ns" { clk {} clk~out0 {} set {} } { 0.000ns 0.000ns 1.984ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.412 ns" { set six:U5|b~158 six:U5|b[0]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.412 ns" { set {} six:U5|b~158 {} six:U5|b[0]$latch {} } { 0.000ns 1.271ns 0.407ns } { 0.000ns 0.292ns 0.442ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}