bidir.map.summary

给大家一些关于VERILOG方面的学习以及练习的资料 主要是代码 希望大家喜欢

Analysis & Synthesis Status : Successful - Sat Mar 15 10:54:58 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : bidir
Top-level Entity Name : bidir
Family : Cyclone
Total logic elements : 1
Total pins : 5
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge