bidir.tan.qmsg

给大家一些关于VERILOG方面的学习以及练习的资料 主要是代码 希望大家喜欢

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 15 10:55:18 2008 " "Info: Processing started: Sat Mar 15 10:55:18 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off bidir -c bidir --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bidir -c bidir --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "tri_inout out 12.016 ns Longest " "Info: Longest tpd from source pin \"tri_inout\" to destination pin \"out\" is 12.016 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tri_inout 1 PIN PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_78; Fanout = 1; PIN Node = 'tri_inout'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { tri_inout } "NODE_NAME" } } { "bidir.v" "" { Text "C:/Documents and Settings/Administrator/桌面/Verilog 130例/chap9/bidir.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns tri_inout~1 2 COMB IOC_X10_Y0_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = IOC_X10_Y0_N1; Fanout = 1; COMB Node = 'tri_inout~1'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.475 ns" { tri_inout tri_inout~1 } "NODE_NAME" } } { "bidir.v" "" { Text "C:/Documents and Settings/Administrator/桌面/Verilog 130例/chap9/bidir.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.023 ns) + CELL(0.292 ns) 6.790 ns out~0 3 COMB LC_X10_Y1_N2 1 " "Info: 3: + IC(5.023 ns) + CELL(0.292 ns) = 6.790 ns; Loc. = LC_X10_Y1_N2; Fanout = 1; COMB Node = 'out~0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.315 ns" { tri_inout~1 out~0 } "NODE_NAME" } } { "bidir.v" "" { Text "C:/Documents and Settings/Administrator/桌面/Verilog 130例/chap9/bidir.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.118 ns) + CELL(2.108 ns) 12.016 ns out 4 PIN PIN_222 0 " "Info: 4: + IC(3.118 ns) + CELL(2.108 ns) = 12.016 ns; Loc. = PIN_222; Fanout = 0; PIN Node = 'out'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.226 ns" { out~0 out } "NODE_NAME" } } { "bidir.v" "" { Text "C:/Documents and Settings/Administrator/桌面/Verilog 130例/chap9/bidir.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.875 ns ( 32.25 % ) " "Info: Total cell delay = 3.875 ns ( 32.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.141 ns ( 67.75 % ) " "Info: Total interconnect delay = 8.141 ns ( 67.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.016 ns" { tri_inout tri_inout~1 out~0 out } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.016 ns" { tri_inout {} tri_inout~1 {} out~0 {} out {} } { 0.000ns 0.000ns 5.023ns 3.118ns } { 0.000ns 1.475ns 0.292ns 2.108ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 15 10:55:21 2008 " "Info: Processing ended: Sat Mar 15 10:55:21 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}