motion_estimation.v

Use verilog and VHDL to implement the Motion Estimation function, work as the hardware accelerator.

always @(posedge clk_sys)
begin
    if (!rst_n)
        pf_db_sam_en <= 1'b0;
    else if ((srh_win_en)&(srh_kb_cnt==4'b0001))
        pf_db_sam_en <= 1'b1;
    else if (srh_kb_cnt==4'b1111)
        pf_db_sam_en <= 1'b0;
end

//generate the addressb increment of block in the search window
always @(posedge clk_sys)
begin
   if (!rst_n)
      srh_l_addr_cntb <= 12'd352;
   else if ((srh_win_en)&(srh_kb_cnt==4'b1111))
   begin
       if (srh_lblk_cnt ==3'b111)
           srh_l_addr_cntb <= 12'd352;
       else
           srh_l_addr_cntb <= srh_l_addr_cntb +12'd704;
   end
end


//generate search window row address
always @(blk_jaddr_starta or srh_blkaddr_lstarta or srh_l_addr_cnta)
begin
    if ((blk_jaddr_starta + srh_blkaddr_lstarta + srh_l_addr_cnta) < 11'd1056)
        srh_win_laddra = 16'h00000;
    else if ((blk_jaddr_starta+srh_blkaddr_lstarta+srh_l_addr_cnta)>16'd98560)
        srh_win_laddra = 16'd98560;
    else
        srh_win_laddra = blk_jaddr_starta - 11'd1056 + srh_blkaddr_lstarta + srh_l_addr_cnta;
end

always @(blk_jaddr_startb or srh_blkaddr_lstartb or srh_l_addr_cntb)
begin
    if ((blk_jaddr_startb + srh_blkaddr_lstartb + srh_l_addr_cntb) < 11'd1056)
        srh_win_laddrb = 16'd0;
    else if ((blk_jaddr_startb+srh_blkaddr_lstartb+srh_l_addr_cntb)>16'd98560)
        srh_win_laddrb = 16'd98560;
    else
        srh_win_laddrb = blk_jaddr_startb - 11'd1056 + srh_blkaddr_lstartb + srh_l_addr_cntb;
end
            
//generate search window row address
always @(blk_i_starta or srh_ka_cnt)
begin
    if ((blk_i_starta + srh_ka_cnt ) < 2'd3)
       srh_win_kaddra = 9'd0;
    else if ((blk_i_starta + srh_ka_cnt ) > 9'd351)
       srh_win_kaddra = 9'd351;
    else
       srh_win_kaddra = blk_i_starta + srh_ka_cnt -2'd3;
end

always @(blk_i_startb or srh_kb_cnt)
begin
    if ((blk_i_startb + srh_kb_cnt ) < 2'd3)
       srh_win_kaddrb = 9'd10;
    else if ((blk_i_startb + srh_kb_cnt ) > 9'd351)
       srh_win_kaddrb = 9'd351;
    else
       srh_win_kaddrb = blk_i_startb + srh_kb_cnt -2'd3;
end

//generate the addressa of previous frame
always @(posedge clk_sys)
begin
   if (!rst_n)
      frm_pf_addra <= 16'h00000;
   else 
      frm_pf_addra <= srh_win_laddra + srh_win_kaddra;
end

always @(posedge clk_sys)
begin
   if (!rst_n)
      frm_pf_addrb <= 16'd352;
   else
   frm_pf_addrb <= srh_win_laddrb + srh_win_kaddrb;
end


//generate the first row address increment of each block in the window
always @(posedge clk_sys)
begin
   if (!rst_n)
   begin
      srh_blkaddr_lstarta <= 12'd0;
      srh_blk_lstarta <= 3'd0;
   end
   else if (srh_win_enda)
   begin
      srh_blkaddr_lstarta <= 12'd0;
      srh_blk_lstarta <= 3'd0;
   end
   else if ((srh_win_en)&(srh_ka_cnt==4'b1111))
   begin
      if (srh_lblk_cnt==3'b110)
      begin
          srh_blkaddr_lstarta <= srh_blkaddr_lstarta +9'd352;
          srh_blk_lstarta <= srh_blk_lstarta + 1'b1;
      end
   end
end

always @(posedge clk_sys)
begin
   if (!rst_n)
   begin
      srh_blkaddr_lstartb <= 12'd0;
      srh_blk_lstartb <= 3'd0;
   end
   else if ((srh_win_en)&(srh_ka_cnt==4'b0111))
   begin
      srh_blkaddr_lstartb <= srh_blkaddr_lstarta;
      srh_blk_lstartb <= srh_blk_lstarta;
   end
end

//gernerate the search window end signal
always @(srh_lblk_cnt or srh_ka_cnt or srh_win_en or srh_blkaddr_lstarta)
begin
    srh_win_enda = ((srh_win_en)&(srh_lblk_cnt==3'b110)&(srh_ka_cnt==4'b1111)&(srh_blkaddr_lstarta==12'd2112));
end        

always @(srh_lblk_cnt or srh_kb_cnt or srh_win_en or srh_blkaddr_lstartb)
begin
    srh_win_endb = ((srh_win_en)&(srh_lblk_cnt==3'b111)&(srh_kb_cnt==4'b1111)&(srh_blkaddr_lstartb==12'd2112));
end 

//generate the one array block end signal
always @(srh_win_en or srh_lblk_cnt or srh_kb_cnt)
begin
    srh_array_end = ((srh_win_en)&(srh_lblk_cnt==3'b111)&(srh_kb_cnt==4'b1111));
end

//***********************************************************************************************//
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//**************************subtration absolute aacumultation compare****************************// 
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//register the data from sram
always @(posedge clk_sys)
begin
    if (!rst_n)
    begin
        cf_d <= 8'h00;
    end
    else if (srh_kb_cnt_en)
        cf_d <= frm_cf_d;
end

always @(posedge clk_sys)
begin
    if (!rst_n)
    begin
        pf_da0 <= 8'h00;
        pf_da1 <= 8'h00;
        pf_da2 <= 8'h00;
        pf_da3 <= 8'h00;
        pf_da4 <= 8'h00;
        pf_da5 <= 8'h00;
        pf_da6 <= 8'h00;
    end
    else if (pf_da_sam_en)
        pf_da6 <= frm_pf_da;
        pf_da5 <= pf_da6;
        pf_da4 <= pf_da5;
        pf_da3 <= pf_da4;
        pf_da2 <= pf_da3;
        pf_da1 <= pf_da2;
        pf_da0 <= pf_da1;
end

always @(posedge clk_sys)
begin
    if (!rst_n)
    begin
        pf_db0 <= 8'h00;
        pf_db1 <= 8'h00;
        pf_db2 <= 8'h00;
        pf_db3 <= 8'h00;
        pf_db4 <= 8'h00;
        pf_db5 <= 8'h00;
        pf_db6 <= 8'h00;
    end
    else if ((pf_db_sam_en)&(srh_kb_cnt_en))
        pf_db6 <= frm_pf_db;
        pf_db5 <= pf_db6;
        pf_db4 <= pf_db5;
        pf_db3 <= pf_db4;
        pf_db2 <= pf_db3;
        pf_db1 <= pf_db2;
        pf_db0 <= pf_db1;
end

//select a or b
always @(srh_k_sel or pf_da0 or pf_da1 or pf_da2 or pf_da3 or pf_da4 or pf_da5 or pf_da6 or pf_db0 or pf_db1 or pf_db2 or pf_db3 or pf_db4 or pf_db5 or pf_db6)
begin
       pf_d0 = srh_k_sel ? pf_da0 : pf_db0;
       pf_d1 = srh_k_sel ? pf_da1 : pf_db1;
       pf_d2 = srh_k_sel ? pf_da2 : pf_db2;
       pf_d3 = srh_k_sel ? pf_da3 : pf_db3;
       pf_d4 = srh_k_sel ? pf_da4 : pf_db4;
       pf_d5 = srh_k_sel ? pf_da5 : pf_db5;
       pf_d6 = srh_k_sel ? pf_da6 : pf_db6;
end


//subtract
always @(cf_d or pf_d0 or pf_d1 or pf_d2 or pf_d3 or pf_d4 or pf_d5 or pf_d6)
begin
    cf_sub_pf0 = cf_d - pf_d0;
    cf_sub_pf1 = cf_d - pf_d1;
    cf_sub_pf2 = cf_d - pf_d2;
    cf_sub_pf3 = cf_d - pf_d3;
    cf_sub_pf4 = cf_d - pf_d4;
    cf_sub_pf5 = cf_d - pf_d5;
    cf_sub_pf6 = cf_d - pf_d6;
end

//absolute
always @(cf_sub_pf0 or cf_sub_pf1 or cf_sub_pf2 or cf_sub_pf3 or cf_sub_pf4 or cf_sub_pf5 or cf_sub_pf6)
begin
    abs_sub0 =cf_sub_pf0[8] ? (~cf_sub_pf0[7:0]+1'b1) : cf_sub_pf0[7:0];
    abs_sub1 =cf_sub_pf1[8] ? (~cf_sub_pf1[7:0]+1'b1) : cf_sub_pf1[7:0];
    abs_sub2 =cf_sub_pf2[8] ? (~cf_sub_pf2[7:0]+1'b1) : cf_sub_pf2[7:0];
    abs_sub3 =cf_sub_pf3[8] ? (~cf_sub_pf3[7:0]+1'b1) : cf_sub_pf3[7:0];
    abs_sub4 =cf_sub_pf4[8] ? (~cf_sub_pf4[7:0]+1'b1) : cf_sub_pf4[7:0];
    abs_sub5 =cf_sub_pf5[8] ? (~cf_sub_pf5[7:0]+1'b1) : cf_sub_pf5[7:0];
    abs_sub6 =cf_sub_pf6[8] ? (~cf_sub_pf6[7:0]+1'b1) : cf_sub_pf6[7:0];
end


//accumulation
always @(posedge clk_sys)
begin
    if (!rst_n)
    begin
        acc_abs_sub0 <= 14'h0000;
        acc_abs_sub1 <= 14'h0000;
        acc_abs_sub2 <= 14'h0000;
        acc_abs_sub3 <= 14'h0000;
        acc_abs_sub4 <= 14'h0000;
        acc_abs_sub5 <= 14'h0000;
        acc_abs_sub6 <= 14'h0000;
    end
    else if (srh_kb_cnt_en_ff)
    begin
        if (srh_array_end)
        begin
            acc_abs_sub0 <= 14'h0000;
            acc_abs_sub1 <= 14'h0000;
            acc_abs_sub2 <= 14'h0000;
            acc_abs_sub3 <= 14'h0000;
            acc_abs_sub4 <= 14'h0000;
            acc_abs_sub5 <= 14'h0000;
            acc_abs_sub6 <= 14'h0000;
        end
        else
        begin
            acc_abs_sub0 <= acc_abs_sub0 + abs_sub0;
            acc_abs_sub1 <= acc_abs_sub1 + abs_sub1;
            acc_abs_sub2 <= acc_abs_sub2 + abs_sub2;
            acc_abs_sub3 <= acc_abs_sub3 + abs_sub3;
            acc_abs_sub4 <= acc_abs_sub4 + abs_sub4;
            acc_abs_sub5 <= acc_abs_sub5 + abs_sub5;
            acc_abs_sub6 <= acc_abs_sub6 + abs_sub6;
        end
    end
end

//register the accumulation
always @(posedge clk_sys)
begin
    if (!rst_n)
    begin
        acc_abs_sub_ff0 <= 14'h0000;
        acc_abs_sub_ff1 <= 14'h0000;
        acc_abs_sub_ff2 <= 14'h0000;
        acc_abs_sub_ff3 <= 14'h0000;
        acc_abs_sub_ff4 <= 14'h0000;
        acc_abs_sub_ff5 <= 14'h0000;
        acc_abs_sub_ff6 <= 14'h0000;
    end
    else if (srh_array_end)
    begin
        acc_abs_sub_ff0 <= acc_abs_sub0;
        acc_abs_sub_ff1 <= acc_abs_sub1;
        acc_abs_sub_ff2 <= acc_abs_sub2;
        acc_abs_sub_ff3 <= acc_abs_sub3;
        acc_abs_sub_ff4 <= acc_abs_sub4;
        acc_abs_sub_ff5 <= acc_abs_sub5;
        acc_abs_sub_ff6 <= acc_abs_sub6;
    end
end

//generate the enable signal for comp_acc
always @(posedge clk_sys)
begin
    if (!rst_n)
        comp_acc_en <= 1'b0;
    else if (srh_array_end)
        comp_acc_en <= 1'b1;
    else if (comp_cnt==3'b110)
        comp_acc_en <= 1'b0;
end

always @(posedge clk_sys)
begin
    if (!rst_n)
       comp_cnt <= 3'b000;
    else if (comp_acc_en)
    begin
        if (comp_cnt==3'b110)
            comp_cnt <= 3'b000;
        else 
            comp_cnt <= comp_cnt + 1'b1;
    end       
end


always @(comp_cnt or acc_abs_sub_ff0 or acc_abs_sub_ff1 or acc_abs_sub_ff2 or acc_abs_sub_ff3 or acc_abs_sub_ff4 or acc_abs_sub_ff5 or acc_abs_sub_ff6)
begin
    case(comp_cnt)
        3'b000   :    comp_acc_op = acc_abs_sub_ff0;
        3'b001   :    comp_acc_op = acc_abs_sub_ff1;
        3'b010   :    comp_acc_op = acc_abs_sub_ff2;
        3'b011   :    comp_acc_op = acc_abs_sub_ff3;
        3'b100   :    comp_acc_op = acc_abs_sub_ff4;
        3'b101   :    comp_acc_op = acc_abs_sub_ff5;
        3'b100   :    comp_acc_op = acc_abs_sub_ff6;
        default  :    comp_acc_op = acc_abs_sub_ff0;
    endcase
end

always @(posedge clk_sys)
begin
    if (!rst_n)
        comp_acc_abs <= 14'h3fff;
    else if (comp_acc_en)
    begin
        if (comp_acc_abs >comp_acc_op)
            comp_acc_abs <= comp_acc_op;
    end
    else if (srh_win_end_cnt==3'b111)
        comp_acc_abs <= 14'h3fff;
end


//generate the enable signal for srh_win_end_cnt
always @(posedge clk_sys)
begin
    if (!rst_n)
        srh_win_end_cnt_en <= 1'b0;
    else if (srh_win_endb)
        srh_win_end_cnt_en <= 1'b1;
    else if (srh_win_end_cnt==3'b111)
        srh_win_end_cnt_en <= 1'b0;
end

always @(posedge clk_sys)
begin
    if (!rst_n)
       srh_win_end_cnt <= 3'b000;
    else if (srh_win_end_cnt_en)
       srh_win_end_cnt <= srh_win_end_cnt + 1'b1;
end


//register the vector collumn
always @(posedge clk_sys)
begin
    if (!rst_n)
       blk_col <= 3'd0;
    else if ((comp_acc_en)&(comp_acc_abs >comp_acc_op))
       blk_col <= comp_cnt;
end

//register the first row address of block
always @(posedge clk_sys)
begin
    if (!rst_n)
        srh_lstartb_ff <= 3'd0;
    else if (srh_array_end)
        srh_lstartb_ff <= srh_blk_lstartb;
end

//register the vector row
always @(posedge clk_sys)
begin
    if (!rst_n)
        blk_row <= 3'd0;
    else if ((comp_acc_en)&(comp_acc_abs >comp_acc_op))
        blk_row <= srh_lstartb_ff;
end

//register the vector address
always @(posedge clk_sys)
begin
    if (!rst_n)
    begin
        vect_row <= 3'd0;
        vect_col <= 3'd0;
    end
    else if (srh_win_end_cnt==3'b111)
    begin
        vect_row <= blk_row;
        vect_col <= blk_col;
    end
end


endmodule