motion_estimation.v

Use verilog and VHDL to implement the Motion Estimation function, work as the hardware accelerator.

//filename :   motion_estimation.v
//author   :   Ray Luo
//date     :   2007.12.25

module motion_estimation(
       clk_sys,
       rst_n,
       frm_start,
       frm_cf_d,
       frm_pf_da,
       frm_pf_db,
       frm_cf_addr,
       frm_cf_rd,
       frm_pf_addra,
       frm_pf_rda,
       frm_pf_addrb,
       frm_pf_rdb,
       vect_row,
       vect_col
);

input            clk_sys;
input            rst_n;
input            frm_start;
input    [7:0]   frm_cf_d;
input    [7:0]   frm_pf_da;
input    [7:0]   frm_pf_db;
output   [15:0]  frm_cf_addr;
output           frm_cf_rd;
output   [15:0]  frm_pf_addra;
output           frm_pf_rda;
output   [15:0]  frm_pf_addrb;
output           frm_pf_rdb;
output   [2:0]   vect_row;
output   [2:0]   vect_col;

wire            clk_sys;           //the clock of system
wire            rst_n;             //the reset signal
wire            frm_start;         //the motion estimation start
wire    [7:0]   frm_cf_d;
wire    [7:0]   frm_pf_da;
wire    [7:0]   frm_pf_db;
reg     [15:0]  frm_cf_addr;              //the address of the current frame's sram
reg     [15:0]  frm_pf_addra;             //the addressa of the previous frame's sram
reg     [15:0]  frm_pf_addrb;             //the addressb of the previous frame's sram
reg     [2:0]   vect_row;                 //the row of the matching best block for transmit
reg     [2:0]   vect_col;                 //the column of the matching best blok for transmit
reg     [15:0]  blk_row;                  //the first row of the matching best block
reg     [8:0]   blk_col;                  //the first column of the matching best blok 
reg             frm_cf_rd;                //read signal for the current frame
reg             frm_pf_rda;               //read signal for the current frame
reg             frm_pf_rdb;               //read signal for the current frame

reg    [8:0]   blk_i_starta;             //the first column of the block in the previous frame a
reg    [8:0]   blk_i_startb;             //the first column of the block in the previous frame b
reg    [8:0]   blk_i_startc;             //the first column of the block in the current frame
reg    [8:0]   blk_j_start;             //the first row of the block in the frame
reg    [2:0]   blk_i_cnt8;              //the cloumn of the block

reg    [11:0]  srh_l_addr_cnta;         //the addressa of the row in the block
reg    [11:0]  srh_l_addr_cntb;         //the addressb of thw row in the block

reg            srh_win_en;              //enable signal for search in the search window

reg            srh_win_enda;            //the end signal for search window when calculate a
reg            srh_win_endb;            //the end signal for search window when calculate b
reg    [11:0]  srh_blkaddr_lstarta;     //the start first row address of block in the search window a  
reg    [11:0]  srh_blkaddr_lstartb;     //the start first row address of block in the search window b 
reg    [2:0]   srh_blk_lstarta;         //the start first row of block int the search window a
reg    [2:0]   srh_blk_lstartb;         //the start first row of block int the search window a
reg    [2:0]   srh_lstartb_ff;          //the start first row address of block in the search window b
                                                                  
reg            frm_start_ff ;           //delay frm_sart signal one cycle       
reg    [15:0]  blk_jaddr_starta;        //the first address of the row a in the previous frame
reg    [15:0]  blk_jaddr_startb;        //the first address of the row b in the previous frame
reg    [15:0]  blk_jaddr_startc;        //the first address of the row in the current frame

reg    [11:0]  blk_jaddr_cnt8;                             
reg    [2:0]   srh_lblk_cnt;            //count the row of one block in the search window    
reg            pf_da_sam_en;            //enable signal for pf_da                                   
reg            pf_db_sam_en;            //enable signal for pf_db                                   

reg    [7:0]   pf_da0;                  //register the previous frame data when read a address
reg    [7:0]   pf_da1;                  //register the previous frame data when read a address
reg    [7:0]   pf_da2;                  //register the previous frame data when read a address
reg    [7:0]   pf_da3;                  //register the previous frame data when read a address
reg    [7:0]   pf_da4;                  //register the previous frame data when read a address
reg    [7:0]   pf_da5;                  //register the previous frame data when read a address
reg    [7:0]   pf_da6;                  //register the previous frame data when read a address
reg    [7:0]   pf_db0;                  //register the previous frame data when read b address
reg    [7:0]   pf_db1;                  //register the previous frame data when read b address
reg    [7:0]   pf_db2;                  //register the previous frame data when read b address
reg    [7:0]   pf_db3;                  //register the previous frame data when read b address
reg    [7:0]   pf_db4;                  //register the previous frame data when read b address
reg    [7:0]   pf_db5;                  //register the previous frame data when read b address
reg    [7:0]   pf_db6;                  //register the previous frame data when read b address
reg    [7:0]   cf_d;                    //register the current frame data 
            
reg    [7:0]   pf_d0;                   //the pixel number come from previous frame
reg    [7:0]   pf_d1;                   //the pixel number come from previous frame
reg    [7:0]   pf_d2;                   //the pixel number come from previous frame
reg    [7:0]   pf_d3;                   //the pixel number come from previous frame
reg    [7:0]   pf_d4;                   //the pixel number come from previous frame
reg    [7:0]   pf_d5;                   //the pixel number come from previous frame
reg    [7:0]   pf_d6;                   //the pixel number come from previous frame
reg    [8:0]   cf_sub_pf0;              //the substraction of two row pixel
reg    [8:0]   cf_sub_pf1;              //the substraction of two row pixel
reg    [8:0]   cf_sub_pf2;              //the substraction of two row pixel
reg    [8:0]   cf_sub_pf3;              //the substraction of two row pixel
reg    [8:0]   cf_sub_pf4;              //the substraction of two row pixel
reg    [8:0]   cf_sub_pf5;              //the substraction of two row pixel
reg    [8:0]   cf_sub_pf6;              //the substraction of two row pixel
reg    [7:0]   abs_sub0;                //absolute the subtract
reg    [7:0]   abs_sub1;                //absolute the subtract
reg    [7:0]   abs_sub2;                //absolute the subtract
reg    [7:0]   abs_sub3;                //absolute the subtract
reg    [7:0]   abs_sub4;                //absolute the subtract
reg    [7:0]   abs_sub5;                //absolute the subtract
reg    [7:0]   abs_sub6;                //absolute the subtract
reg    [13:0]  acc_abs_sub0;            //accumulation register for abs_sub
reg    [13:0]  acc_abs_sub1;            //accumulation register for abs_sub
reg    [13:0]  acc_abs_sub2;            //accumulation register for abs_sub
reg    [13:0]  acc_abs_sub3;            //accumulation register for abs_sub
reg    [13:0]  acc_abs_sub4;            //accumulation register for abs_sub
reg    [13:0]  acc_abs_sub5;            //accumulation register for abs_sub
reg    [13:0]  acc_abs_sub6;            //accumulation register for abs_sub
reg    [13:0]  acc_abs_sub_ff0;         //delay accumulation register for abs_sub
reg    [13:0]  acc_abs_sub_ff1;         //delay accumulation register for abs_sub
reg    [13:0]  acc_abs_sub_ff2;         //delay accumulation register for abs_sub
reg    [13:0]  acc_abs_sub_ff3;         //delay accumulation register for abs_sub
reg    [13:0]  acc_abs_sub_ff4;         //delay accumulation register for abs_sub
reg    [13:0]  acc_abs_sub_ff5;         //delay accumulation register for abs_sub
reg    [13:0]  acc_abs_sub_ff6;         //delay accumulation register for abs_sub
reg    [13:0]  comp_acc_op;             //one option number for compare         
reg    [13:0]  comp_acc_abs;            //register for the minimus accumulation 
reg            comp_acc_en ;            //enable signal for compare accumulation
reg    [3:0]   srh_ka_cnt;              //counter for the a collumn of the block in the window   
reg    [3:0]   srh_kb_cnt;              //counter for the b collumn of the block in the window   
reg            srh_kb_cnt_en;           //enable the srh_kb_cnt
reg            srh_kb_cnt_en_ff;        //delay srh_kb_cnt one cycle                                  
reg            srh_k_sel;               //select signal for srh_ka_cnt and srh_kb_cnt            
reg    [2:0]   comp_cnt;                //counter for compare             

reg    [15:0]  srh_win_laddra;          //search window row addressa
reg    [15:0]  srh_win_laddrb;          //search window row addressb
reg    [7:0]   srh_win_kaddra;          //search window column addressa
reg    [7:0]   srh_win_kaddrb;          //search window column addressa
reg            srh_array_end;           //one array block end signal

reg    [2:0]   srh_win_end_cnt;         //the counter after end signal generate 
reg            srh_win_end_cnt_en;      //the enable signal for srh_win_end_cnt

reg            blk_i_cnt8_en;           //enable signal for blk_i_cnt8
integer        i;

//****************************control the address of current frame*******************************//
//***********************************************************************************************//
//***********************************************************************************************//
//***********************************************************************************************//
//***********************************************************************************************//
//register the frame start signal
always @(posedge clk_sys)
begin
    if (!rst_n)
        frm_start_ff <= 1'b0;
    else if (frm_start)
        frm_start_ff <= 1'b1;
    else if ((blk_jaddr_startb==16'd98560)&(blk_i_startb==9'd344)&srh_win_endb)
       frm_start_ff <= 1'b0;
end

always @(posedge clk_sys)
begin
    if (!rst_n)
        frm_cf_rd <= 1'b1;
    else if (frm_start)
        frm_cf_rd <= 1'b0;
end

always @(posedge clk_sys)
begin
    if (!rst_n)
        frm_pf_rda <= 1'b1;
    else if (frm_start)
        frm_pf_rda <= 1'b0;
end

always @(posedge clk_sys)
begin
    if (!rst_n)
        frm_pf_rdb <= 1'b1;
    else if (frm_start)
        frm_pf_rdb <= 1'b0;
end


//register the frm_start_ff
always @(posedge clk_sys)
begin
    if (!rst_n)
        srh_win_en <= 1'b0;
    else
        srh_win_en <= frm_start_ff;
end

//genrate the first column of the block a
always  @(posedge clk_sys)
begin
   if (!rst_n)
      blk_i_starta <= 9'd0;
   else if (!frm_start_ff)
      blk_i_starta <= 9'd0;
   else if (frm_start_ff&srh_win_enda)
   begin
      if (blk_i_starta==9'd344)
          blk_i_starta <= 9'd0;
      else 
          blk_i_starta <= blk_i_starta+1;
   end 
end

//genrate the first row of the block
always @(posedge clk_sys)
begin
   if (!rst_n)
      blk_j_start <= 9'd0;
   else if (frm_start_ff)
   begin 
      if ((blk_i_starta==9'd344)&srh_win_enda)
         blk_j_start <= blk_j_start + 1'b1;
   end
end


//generate address of the first row in the block a
always @(posedge clk_sys)
begin
   if (!rst_n)
      blk_jaddr_starta <= 16'd0;
   else if (frm_start_ff)
   begin 
      if ((blk_i_starta==9'd344)&srh_win_enda)
         blk_jaddr_starta <= blk_jaddr_starta + 9'd352;
   end
end   

//generate address of the first row in the block b
always @(posedge clk_sys)
begin
   if (!rst_n)
   begin
      blk_jaddr_startb <= 16'd0;
      blk_i_startb <= 9'd0;
   end
   else if (!frm_start_ff)
   begin
      blk_jaddr_startb <= 16'd0;
      blk_i_startb <= 9'd0;
   end 
   else if ((srh_ka_cnt==4'b0111)&frm_start_ff)
   begin
      blk_jaddr_startb <= blk_jaddr_starta;
      blk_i_startb <= blk_i_starta;
   end
end  

//generate address of the first row in the block b
always @(posedge clk_sys)
begin
   if (!rst_n)
   begin
      blk_jaddr_startc <= 16'd0;
      blk_i_startc <= 9'd0;
   end
   else if (!frm_start_ff)
   begin
      blk_jaddr_startc <= 16'd0;
      blk_i_startc <= 9'd0;
   end 
   else if ((srh_ka_cnt==4'b0101)&frm_start_ff)
   begin
      blk_jaddr_startc <= blk_jaddr_starta;
      blk_i_startc <= blk_i_starta;
   end
end  

//generate the cloumn of the block for substract
always @(posedge clk_sys)
begin
   if (!rst_n)
      blk_i_cnt8 <= 3'b000;
   else if (blk_i_cnt8_en)
      blk_i_cnt8 <= blk_i_cnt8+1'b1;
end

//generate the row address increment of block
always @(posedge clk_sys)
begin
   if (!rst_n)
      blk_jaddr_cnt8 <= 12'd0;
   else if ((blk_jaddr_cnt8 ==12'd2464)&(blk_i_cnt8==3'b111))
      blk_jaddr_cnt8 <= 12'd0;
   else if (blk_i_cnt8==3'b111)
      blk_jaddr_cnt8 <= blk_jaddr_cnt8 +9'd352;
end

//generate the address of current frame
always @(posedge clk_sys)
begin
   if (!rst_n)
      frm_cf_addr <= 16'h00000;
   else
      frm_cf_addr <= blk_jaddr_startc + blk_jaddr_cnt8 + blk_i_cnt8 + blk_i_startc;
end

//***********************************************************************************************//
//***********************************************************************************************//
//***********************************************************************************************//
//***********************************************************************************************//

     
     
//**************************control the address of previous frame********************************// 
//***********************************************************************************************//
//***********************************************************************************************//
//***********************************************************************************************//
//***********************************************************************************************//


//*****************************control one block in the window***********************************//
//***********************************************************************************************//
//generate the address of columna in the search window
always @(posedge clk_sys)
begin
   if (!rst_n)
      srh_ka_cnt <= 4'b0000;
   else if (srh_win_en)
      srh_ka_cnt <= srh_ka_cnt + 1'b1;
   else 
      srh_ka_cnt <= 4'b0000;
end

//generate the enable signal for blk_i_cnt8_en
always @(posedge clk_sys)
begin
   if (!rst_n)
      blk_i_cnt8_en <= 1'b0;
   else if (srh_win_en&(srh_ka_cnt==4'b0101))
      blk_i_cnt8_en <= 1'b1;
   else if (!srh_win_en)
      blk_i_cnt8_en <= 1'b0;
end

//generate the enable signal for srh_kb_cnt
always @(posedge clk_sys)
begin
   if (!rst_n)
      srh_kb_cnt_en <= 1'b0;
   else if (srh_win_en&(srh_ka_cnt==4'b0111))
      srh_kb_cnt_en <= 1'b1;
   else if (!srh_win_en)
      srh_kb_cnt_en <= 1'b0;
end

//delay srh_kb_cnt_en one cycle
always @(posedge clk_sys)
begin
    if (!rst_n)
       srh_kb_cnt_en_ff <= 1'b0;
    else
       srh_kb_cnt_en_ff <= srh_kb_cnt_en;
end

//generate the address of columna in the search window
always @(posedge clk_sys)
begin
   if (!rst_n)
      srh_kb_cnt <= 4'b0000;
   else if (srh_kb_cnt_en)
      srh_kb_cnt <= srh_kb_cnt + 1'b1;
   else 
      srh_kb_cnt <= 4'b0000;
end

//generate the select signal for the row of search window block
always @(posedge clk_sys)
begin
   if (!rst_n)
       srh_k_sel <= 1'b0;
   else if ((srh_win_en)&(srh_ka_cnt==4'b1000))
       srh_k_sel <= 1'b1;
   else if ((srh_win_en)&(srh_kb_cnt==4'b1000))
       srh_k_sel <= 1'b0;
   else if (!srh_win_en)
       srh_k_sel <= 1'b0;
end


//generate the row of one block in the search window
always @(posedge clk_sys)
begin
   if (!rst_n)
      srh_lblk_cnt <= 3'b000;
   else if ((srh_win_en)&((srh_ka_cnt==4'b1111)|(srh_kb_cnt==4'b1111)))
      srh_lblk_cnt <= srh_lblk_cnt + 1'b1;
end

//generate the addressa increment of block in the search window
always @(posedge clk_sys)
begin
   if (!rst_n)
      srh_l_addr_cnta <= 12'd0;
   else if ((srh_win_en)&(srh_ka_cnt==4'b1111))
   begin 
       if (srh_lblk_cnt ==3'b110)
           srh_l_addr_cnta <= 12'd0;
       else 
           srh_l_addr_cnta <= srh_l_addr_cnta +12'd704;
   end
end

//generate the data enable signal
always @(posedge clk_sys)
begin
    if (!rst_n)
        pf_da_sam_en <= 1'b0;
    else if ((srh_win_en)&(srh_ka_cnt==4'b0001))
        pf_da_sam_en <= 1'b1;
    else if (srh_ka_cnt==4'b1111)
        pf_da_sam_en <= 1'b0;
end