basic_unit_package.vhd

来自「Use verilog and VHDL to implement the Mo」· VHDL 代码 · 共 42 行

library IEEE; 
use IEEE.std_logic_1164.all; 


package basic_unit_package is    
    
    function to_integer(bin : std_logic_vector) return integer;    
    function int2bin(int, n : integer) return std_logic_vector;

end basic_unit_package;

package body basic_unit_package is
    -- convert binary to integer   
    function to_integer(bin : std_logic_vector) return integer is
        constant n : integer := bin'length;
        constant max : integer := (2**(n-1));
        variable result : integer;
    begin
        result := 0;
        for i in bin'range loop
            if bin(i) = '1' then
                result := result + 2**i;
            end if;
        end loop;
        return result;
    end to_integer;    
    function int2bin (int, n : integer) return std_logic_vector is
        variable tmp : integer;
        variable bin : std_logic_vector((n-1) downto 0);
    begin
        tmp := int;
        for i in 0 to (n-1) loop
            if (tmp mod 2 = 1) then
                bin(i) := '1';
            else    bin(i) := '0';
            end if;
            tmp := tmp/2;
        end loop;
        return bin;    
    end int2bin;    
end basic_unit_package;