mul18.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    10:07:12 04/09/08
-- Design Name:    
-- Module Name:    mul18 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul18 is
	port(
		mul18_in:in std_logic_vector(12 downto 0);	  --msb_lsb
		mul18_out:out std_logic_vector(12 downto 0)
		);
end mul18;

architecture Behavioral of mul18 is

begin

mul18_out(0)<=mul18_in(5) xor mul18_in(8) xor mul18_in(4) xor mul18_in(7);
mul18_out(1)<=mul18_in(7) xor mul18_in(4) xor mul18_in(6) xor mul18_in(9);
mul18_out(2)<=mul18_in(5) xor mul18_in(7) xor mul18_in(8) xor mul18_in(10);
mul18_out(3)<=mul18_in(9) xor mul18_in(4) xor mul18_in(6) xor mul18_in(5) xor mul18_in(11) xor mul18_in(7);
mul18_out(4)<=mul18_in(12) xor mul18_in(10) xor mul18_in(4) xor mul18_in(6);
mul18_out(5)<=mul18_in(0) xor mul18_in(11) xor mul18_in(7) xor mul18_in(5);
mul18_out(6)<=mul18_in(6) xor mul18_in(12) xor mul18_in(8) xor mul18_in(1) xor mul18_in(0);
mul18_out(7)<=mul18_in(7) xor mul18_in(9) xor mul18_in(2) xor mul18_in(1);
mul18_out(8)<=mul18_in(3) xor mul18_in(10) xor mul18_in(8) xor mul18_in(2) xor mul18_in(0);
mul18_out(9)<=mul18_in(1) xor mul18_in(11) xor mul18_in(0) xor mul18_in(9) xor mul18_in(3) xor mul18_in(4);
mul18_out(10)<=mul18_in(2) xor mul18_in(5) xor mul18_in(4) xor mul18_in(12) xor mul18_in(1) xor mul18_in(10);
mul18_out(11)<=mul18_in(11) xor mul18_in(3) xor mul18_in(5) xor mul18_in(6) xor mul18_in(2);
mul18_out(12)<=mul18_in(4) xor mul18_in(6) xor mul18_in(12) xor mul18_in(7) xor mul18_in(3);

end Behavioral;