mul88.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    20:38:59 04/01/08
-- Design Name:    
-- Module Name:    mul88 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul88 is
port(
	mul88_in:in std_logic_vector(12 downto 0);	  --msb_lsb
	mul88_out:out std_logic_vector(12 downto 0)
	);
end mul88;

architecture Behavioral of mul88 is

begin

mul88_out(0)<=mul88_in(4) xor mul88_in(5) xor mul88_in(0);
mul88_out(1)<=mul88_in(1) xor mul88_in(4) xor mul88_in(6);
mul88_out(2)<=mul88_in(2) xor mul88_in(7) xor mul88_in(5);
mul88_out(3)<=mul88_in(5) xor mul88_in(6) xor mul88_in(3) xor mul88_in(4) xor mul88_in(8);
mul88_out(4)<=mul88_in(9) xor mul88_in(6) xor mul88_in(7);
mul88_out(5)<=mul88_in(7) xor mul88_in(10) xor mul88_in(8);
mul88_out(6)<=mul88_in(11) xor mul88_in(8) xor mul88_in(9);
mul88_out(7)<=mul88_in(9) xor mul88_in(10) xor mul88_in(12);
mul88_out(8)<=mul88_in(0) xor mul88_in(10) xor mul88_in(11);
mul88_out(9)<=mul88_in(12) xor mul88_in(11) xor mul88_in(0) xor mul88_in(1);
mul88_out(10)<=mul88_in(2) xor mul88_in(12) xor mul88_in(1);
mul88_out(11)<=mul88_in(3) xor mul88_in(2);
mul88_out(12)<=mul88_in(4) xor mul88_in(3);

end Behavioral;