mul4.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    10:04:06 04/09/08
-- Design Name:    
-- Module Name:    mul4 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul4 is
		port(
		mul4_in:in std_logic_vector(12 downto 0);	  --msb_lsb
		mul4_out:out std_logic_vector(12 downto 0)
	);
end mul4;

architecture Behavioral of mul4 is

begin

mul4_out(0)<=mul4_in(9);
mul4_out(1)<=mul4_in(9) xor mul4_in(10);
mul4_out(2)<=mul4_in(11) xor mul4_in(10);
mul4_out(3)<=mul4_in(11) xor mul4_in(9) xor mul4_in(12);
mul4_out(4)<=mul4_in(12) xor mul4_in(0) xor mul4_in(10) xor mul4_in(9);
mul4_out(5)<=mul4_in(11) xor mul4_in(10) xor mul4_in(1);
mul4_out(6)<=mul4_in(2) xor mul4_in(12) xor mul4_in(11);
mul4_out(7)<=mul4_in(3) xor mul4_in(12);
mul4_out(8)<=mul4_in(4);
mul4_out(9)<=mul4_in(5);
mul4_out(10)<=mul4_in(6);
mul4_out(11)<=mul4_in(7);
mul4_out(12)<=mul4_in(8);


end Behavioral;