mul7.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    10:05:02 04/09/08
-- Design Name:    
-- Module Name:    mul7 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul7 is
		port(
			mul7_in:in std_logic_vector(12 downto 0);	  --msb_lsb
			mul7_out:out std_logic_vector(12 downto 0)
			);
end mul7;

architecture Behavioral of mul7 is

begin

mul7_out(0)<=mul7_in(6);
mul7_out(1)<=mul7_in(6) xor mul7_in(7);
mul7_out(2)<=mul7_in(8) xor mul7_in(7);
mul7_out(3)<=mul7_in(6) xor mul7_in(8) xor mul7_in(9);
mul7_out(4)<=mul7_in(7) xor mul7_in(9) xor mul7_in(10) xor mul7_in(6);
mul7_out(5)<=mul7_in(11) xor mul7_in(10) xor mul7_in(8) xor mul7_in(7);
mul7_out(6)<=mul7_in(11) xor mul7_in(9) xor mul7_in(12) xor mul7_in(8);
mul7_out(7)<=mul7_in(12) xor mul7_in(0) xor mul7_in(10) xor mul7_in(9);
mul7_out(8)<=mul7_in(11) xor mul7_in(10) xor mul7_in(1);
mul7_out(9)<=mul7_in(2) xor mul7_in(12) xor mul7_in(11);
mul7_out(10)<=mul7_in(3) xor mul7_in(12);
mul7_out(11)<=mul7_in(4);
mul7_out(12)<=mul7_in(5);

end Behavioral;