mul1.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    10:03:19 04/09/08
-- Design Name:    
-- Module Name:    mul1 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul1 is
port(
		mul1_in:in std_logic_vector(12 downto 0);	  --msb_lsb
		mul1_out:out std_logic_vector(12 downto 0)
		);
end mul1;

architecture Behavioral of mul1 is

begin

mul1_out(0)<=mul1_in(12);
mul1_out(1)<=mul1_in(12) xor mul1_in(0);
mul1_out(2)<=mul1_in(1);
mul1_out(3)<=mul1_in(2) xor mul1_in(12);
mul1_out(4)<=mul1_in(3) xor mul1_in(12);
mul1_out(5)<=mul1_in(4);
mul1_out(6)<=mul1_in(5);
mul1_out(7)<=mul1_in(6);
mul1_out(8)<=mul1_in(7);
mul1_out(9)<=mul1_in(8);
mul1_out(10)<=mul1_in(9);
mul1_out(11)<=mul1_in(10);
mul1_out(12)<=mul1_in(11);

end Behavioral;