mul96.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    20:39:15 04/01/08
-- Design Name:    
-- Module Name:    mul96 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul96 is
port(
	mul96_in:in std_logic_vector(12 downto 0);	  --msb_lsb
	mul96_out:out std_logic_vector(12 downto 0)
	);
end mul96;

architecture Behavioral of mul96 is

begin

mul96_out(0)<=mul96_in(7) xor mul96_in(10) xor mul96_in(8);
mul96_out(1)<=mul96_in(11) xor mul96_in(7) xor mul96_in(9) xor mul96_in(10);
mul96_out(2)<=mul96_in(12) xor mul96_in(8) xor mul96_in(11) xor mul96_in(10);
mul96_out(3)<=mul96_in(12) xor mul96_in(11) xor mul96_in(0) xor mul96_in(8) xor mul96_in(7) xor mul96_in(9) xor mul96_in(10);
mul96_out(4)<=mul96_in(12) xor mul96_in(9) xor mul96_in(1) xor mul96_in(11) xor mul96_in(7);
mul96_out(5)<=mul96_in(0) xor mul96_in(12) xor mul96_in(2) xor mul96_in(8) xor mul96_in(10);
mul96_out(6)<=mul96_in(1) xor mul96_in(0) xor mul96_in(11) xor mul96_in(9) xor mul96_in(3);
mul96_out(7)<=mul96_in(2) xor mul96_in(10) xor mul96_in(12) xor mul96_in(4) xor mul96_in(1);
mul96_out(8)<=mul96_in(3) xor mul96_in(11) xor mul96_in(5) xor mul96_in(2);
mul96_out(9)<=mul96_in(12) xor mul96_in(4) xor mul96_in(6) xor mul96_in(3);
mul96_out(10)<=mul96_in(5) xor mul96_in(4) xor mul96_in(7);
mul96_out(11)<=mul96_in(5) xor mul96_in(6) xor mul96_in(8);
mul96_out(12)<=mul96_in(9) xor mul96_in(6) xor mul96_in(7);

end Behavioral;