mul20.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    10:07:41 04/09/08
-- Design Name:    
-- Module Name:    mul20 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul20 is
		port(
		mul20_in:in std_logic_vector(12 downto 0);	  --msb_lsb
		mul20_out:out std_logic_vector(12 downto 0)
		);
end mul20;

architecture Behavioral of mul20 is

begin

mul20_out(0)<=mul20_in(3) xor mul20_in(11) xor mul20_in(2) xor mul20_in(5) xor mul20_in(6);
mul20_out(1)<=mul20_in(11) xor mul20_in(2) xor mul20_in(7) xor mul20_in(12) xor mul20_in(5) xor mul20_in(4);
mul20_out(2)<=mul20_in(8) xor mul20_in(3) xor mul20_in(12) xor mul20_in(5) xor mul20_in(6);
mul20_out(3)<=mul20_in(11) xor mul20_in(3) xor mul20_in(9) xor mul20_in(5) xor mul20_in(7) xor mul20_in(2) xor mul20_in(4);
mul20_out(4)<=mul20_in(12) xor mul20_in(8) xor mul20_in(11) xor mul20_in(10) xor mul20_in(4) xor mul20_in(2);
mul20_out(5)<=mul20_in(11) xor mul20_in(5) xor mul20_in(9) xor mul20_in(12) xor mul20_in(3);
mul20_out(6)<=mul20_in(12) xor mul20_in(10) xor mul20_in(4) xor mul20_in(6);
mul20_out(7)<=mul20_in(0) xor mul20_in(11) xor mul20_in(7) xor mul20_in(5);
mul20_out(8)<=mul20_in(6) xor mul20_in(12) xor mul20_in(8) xor mul20_in(1) xor mul20_in(0);
mul20_out(9)<=mul20_in(7) xor mul20_in(9) xor mul20_in(2) xor mul20_in(1);
mul20_out(10)<=mul20_in(3) xor mul20_in(10) xor mul20_in(8) xor mul20_in(2) xor mul20_in(0);
mul20_out(11)<=mul20_in(1) xor mul20_in(11) xor mul20_in(0) xor mul20_in(9) xor mul20_in(3) xor mul20_in(4);
mul20_out(12)<=mul20_in(2) xor mul20_in(5) xor mul20_in(4) xor mul20_in(12) xor mul20_in(1) xor mul20_in(10);

end Behavioral;