mul0.vhd

在gf(2^13)中

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-- Company: 
-- Engineer:
--
-- Create Date:    10:12:25 04/09/08
-- Design Name:    
-- Module Name:    mul0 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mul0 is
	port(
	mul0_in:in std_logic_vector(12 downto 0);	  --msb_lsb
	mul0_out:out std_logic_vector(12 downto 0)
	);
end mul0;

architecture Behavioral of mul0 is

begin

mul0_out(0)<=mul0_in(0);
mul0_out(1)<=mul0_in(1);
mul0_out(2)<=mul0_in(2);
mul0_out(3)<=mul0_in(3);
mul0_out(4)<=mul0_in(4);
mul0_out(5)<=mul0_in(5);
mul0_out(6)<=mul0_in(6);
mul0_out(7)<=mul0_in(7);
mul0_out(8)<=mul0_in(8);
mul0_out(9)<=mul0_in(9);
mul0_out(10)<=mul0_in(10);
mul0_out(11)<=mul0_in(11);
mul0_out(12)<=mul0_in(12);


end Behavioral;