ram_256.map.qmsg

在Quartus中实现256的RAM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 10:55:47 2007 " "Info: Processing started: Thu May 31 10:55:47 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ram_256 -c ram_256 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ram_256 -c ram_256" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_256.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ram_256.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram_256-a " "Info: Found design unit 1: ram_256-a" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ram_256 " "Info: Found entity 1: ram_256" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ram_256 " "Info: Elaborating entity \"ram_256\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_CONST_VALUE_OVERFLOW" "ram_256.vhd(17) " "Warning (10639): VHDL warning at ram_256.vhd(17): constant value overflow" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 17 0 0 } }  } 0 10639 "VHDL warning at %1!s!: constant value overflow" 0 0}
{ "Warning" "WVRFX_VHDL_NOW_NOT_SUPPORTED" "standard.vhd(71) " "Warning (10350): VHDL warning at standard.vhd(71): ignored VHDL standard library NOW function, which is not supported for synthesis" {  } { { "d:/libraries/vhdl/std/standard.vhd" "" { Text "d:/libraries/vhdl/std/standard.vhd" 71 0 0 } }  } 0 10350 "VHDL warning at %1!s!: ignored VHDL standard library NOW function, which is not supported for synthesis" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sram ram_256.vhd(40) " "Warning (10492): VHDL Process Statement warning at ram_256.vhd(40): signal \"sram\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "adr_in ram_256.vhd(40) " "Warning (10492): VHDL Process Statement warning at ram_256.vhd(40): signal \"adr_in\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "7 " "Warning: Design contains 7 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "adr\[1\] " "Warning: No output dependent on input pin \"adr\[1\]\"" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "adr\[2\] " "Warning: No output dependent on input pin \"adr\[2\]\"" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "adr\[3\] " "Warning: No output dependent on input pin \"adr\[3\]\"" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "adr\[4\] " "Warning: No output dependent on input pin \"adr\[4\]\"" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "adr\[5\] " "Warning: No output dependent on input pin \"adr\[5\]\"" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "adr\[6\] " "Warning: No output dependent on input pin \"adr\[6\]\"" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "adr\[7\] " "Warning: No output dependent on input pin \"adr\[7\]\"" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "37 " "Info: Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "10 " "Info: Implemented 10 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 10:55:49 2007 " "Info: Processing ended: Thu May 31 10:55:49 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}