ram_256.tan.qmsg

在Quartus中实现256的RAM

{ "Info" "ITDB_FULL_TCO_RESULT" "we data_out\[4\] sram\[0\]\[4\] 6.687 ns register " "Info: tco from clock \"we\" to destination pin \"data_out\[4\]\" through register \"sram\[0\]\[4\]\" is 6.687 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "we source 2.733 ns + Longest register " "Info: + Longest clock path from clock \"we\" to source register is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns we 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'we'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { we } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.711 ns) 2.733 ns sram\[0\]\[4\] 2 REG LC_X6_Y1_N6 1 " "Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X6_Y1_N6; Fanout = 1; REG Node = 'sram\[0\]\[4\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "1.264 ns" { we sram[0][4] } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.77 % ) " "Info: Total cell delay = 2.180 ns ( 79.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 20.23 % ) " "Info: Total interconnect delay = 0.553 ns ( 20.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "2.733 ns" { we sram[0][4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.733 ns" { we we~out0 sram[0][4] } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.730 ns + Longest register pin " "Info: + Longest register to pin delay is 3.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sram\[0\]\[4\] 1 REG LC_X6_Y1_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N6; Fanout = 1; REG Node = 'sram\[0\]\[4\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { sram[0][4] } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.622 ns) + CELL(2.108 ns) 3.730 ns data_out\[4\] 2 PIN PIN_40 0 " "Info: 2: + IC(1.622 ns) + CELL(2.108 ns) = 3.730 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'data_out\[4\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "3.730 ns" { sram[0][4] data_out[4] } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 56.51 % ) " "Info: Total cell delay = 2.108 ns ( 56.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.622 ns ( 43.49 % ) " "Info: Total interconnect delay = 1.622 ns ( 43.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "3.730 ns" { sram[0][4] data_out[4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "3.730 ns" { sram[0][4] data_out[4] } { 0.000ns 1.622ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "2.733 ns" { we sram[0][4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.733 ns" { we we~out0 sram[0][4] } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "3.730 ns" { sram[0][4] data_out[4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "3.730 ns" { sram[0][4] data_out[4] } { 0.000ns 1.622ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "cs data_out\[5\] 11.661 ns Longest " "Info: Longest tpd from source pin \"cs\" to destination pin \"data_out\[5\]\" is 11.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns cs 1 PIN PIN_139 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_139; Fanout = 2; PIN Node = 'cs'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { cs } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.072 ns) + CELL(0.292 ns) 7.839 ns process1~0 2 COMB LC_X6_Y1_N0 8 " "Info: 2: + IC(6.072 ns) + CELL(0.292 ns) = 7.839 ns; Loc. = LC_X6_Y1_N0; Fanout = 8; COMB Node = 'process1~0'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "6.364 ns" { cs process1~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.743 ns) + CELL(2.079 ns) 11.661 ns data_out\[5\] 3 PIN PIN_37 0 " "Info: 3: + IC(1.743 ns) + CELL(2.079 ns) = 11.661 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'data_out\[5\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "3.822 ns" { process1~0 data_out[5] } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.846 ns ( 32.98 % ) " "Info: Total cell delay = 3.846 ns ( 32.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.815 ns ( 67.02 % ) " "Info: Total interconnect delay = 7.815 ns ( 67.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "11.661 ns" { cs process1~0 data_out[5] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "11.661 ns" { cs cs~out0 process1~0 data_out[5] } { 0.000ns 0.000ns 6.072ns 1.743ns } { 0.000ns 1.475ns 0.292ns 2.079ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sram\[0\]\[0\] we we -1.728 ns register " "Info: th for register \"sram\[0\]\[0\]\" (data pin = \"we\", clock pin = \"we\") is -1.728 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "we destination 2.733 ns + Longest register " "Info: + Longest clock path from clock \"we\" to destination register is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns we 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'we'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { we } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.711 ns) 2.733 ns sram\[0\]\[0\] 2 REG LC_X6_Y1_N3 1 " "Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X6_Y1_N3; Fanout = 1; REG Node = 'sram\[0\]\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "1.264 ns" { we sram[0][0] } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.77 % ) " "Info: Total cell delay = 2.180 ns ( 79.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 20.23 % ) " "Info: Total interconnect delay = 0.553 ns ( 20.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "2.733 ns" { we sram[0][0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.733 ns" { we we~out0 sram[0][0] } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.476 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.476 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns we 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'we'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { we } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.590 ns) 3.154 ns sram\[0\]\[0\]~45 2 COMB LC_X6_Y1_N2 8 " "Info: 2: + IC(1.095 ns) + CELL(0.590 ns) = 3.154 ns; Loc. = LC_X6_Y1_N2; Fanout = 8; COMB Node = 'sram\[0\]\[0\]~45'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "1.685 ns" { we sram[0][0]~45 } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.867 ns) 4.476 ns sram\[0\]\[0\] 3 REG LC_X6_Y1_N3 1 " "Info: 3: + IC(0.455 ns) + CELL(0.867 ns) = 4.476 ns; Loc. = LC_X6_Y1_N3; Fanout = 1; REG Node = 'sram\[0\]\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "1.322 ns" { sram[0][0]~45 sram[0][0] } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.926 ns ( 65.37 % ) " "Info: Total cell delay = 2.926 ns ( 65.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.550 ns ( 34.63 % ) " "Info: Total interconnect delay = 1.550 ns ( 34.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "4.476 ns" { we sram[0][0]~45 sram[0][0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.476 ns" { we we~out0 sram[0][0]~45 sram[0][0] } { 0.000ns 0.000ns 1.095ns 0.455ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "2.733 ns" { we sram[0][0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.733 ns" { we we~out0 sram[0][0] } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "4.476 ns" { we sram[0][0]~45 sram[0][0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.476 ns" { we we~out0 sram[0][0]~45 sram[0][0] } { 0.000ns 0.000ns 1.095ns 0.455ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 10:55:57 2007 " "Info: Processing ended: Thu May 31 10:55:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}