ram_256.tan.qmsg

在Quartus中实现256的RAM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 10:55:56 2007 " "Info: Processing started: Thu May 31 10:55:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off ram_256 -c ram_256 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ram_256 -c ram_256 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "we " "Info: Assuming node \"we\" is an undefined clock" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "we" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "we " "Info: No valid register-to-register data paths exist for clock \"we\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sram\[0\]\[0\] cs we 6.463 ns register " "Info: tsu for register \"sram\[0\]\[0\]\" (data pin = \"cs\", clock pin = \"we\") is 6.463 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.159 ns + Longest pin register " "Info: + Longest pin to register delay is 9.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns cs 1 PIN PIN_139 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_139; Fanout = 2; PIN Node = 'cs'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { cs } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.070 ns) + CELL(0.292 ns) 7.837 ns sram\[0\]\[0\]~45 2 COMB LC_X6_Y1_N2 8 " "Info: 2: + IC(6.070 ns) + CELL(0.292 ns) = 7.837 ns; Loc. = LC_X6_Y1_N2; Fanout = 8; COMB Node = 'sram\[0\]\[0\]~45'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "6.362 ns" { cs sram[0][0]~45 } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.867 ns) 9.159 ns sram\[0\]\[0\] 3 REG LC_X6_Y1_N3 1 " "Info: 3: + IC(0.455 ns) + CELL(0.867 ns) = 9.159 ns; Loc. = LC_X6_Y1_N3; Fanout = 1; REG Node = 'sram\[0\]\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "1.322 ns" { sram[0][0]~45 sram[0][0] } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.634 ns ( 28.76 % ) " "Info: Total cell delay = 2.634 ns ( 28.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.525 ns ( 71.24 % ) " "Info: Total interconnect delay = 6.525 ns ( 71.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "9.159 ns" { cs sram[0][0]~45 sram[0][0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "9.159 ns" { cs cs~out0 sram[0][0]~45 sram[0][0] } { 0.000ns 0.000ns 6.070ns 0.455ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "we destination 2.733 ns - Shortest register " "Info: - Shortest clock path from clock \"we\" to destination register is 2.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns we 1 CLK PIN_17 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'we'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { we } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.711 ns) 2.733 ns sram\[0\]\[0\] 2 REG LC_X6_Y1_N3 1 " "Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X6_Y1_N3; Fanout = 1; REG Node = 'sram\[0\]\[0\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "1.264 ns" { we sram[0][0] } "NODE_NAME" } "" } } { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.77 % ) " "Info: Total cell delay = 2.180 ns ( 79.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.553 ns ( 20.23 % ) " "Info: Total interconnect delay = 0.553 ns ( 20.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "2.733 ns" { we sram[0][0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.733 ns" { we we~out0 sram[0][0] } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "9.159 ns" { cs sram[0][0]~45 sram[0][0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "9.159 ns" { cs cs~out0 sram[0][0]~45 sram[0][0] } { 0.000ns 0.000ns 6.070ns 0.455ns } { 0.000ns 1.475ns 0.292ns 0.867ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "2.733 ns" { we sram[0][0] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.733 ns" { we we~out0 sram[0][0] } { 0.000ns 0.000ns 0.553ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}