ram_256.sim.qmsg

在Quartus中实现256的RAM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 16 16:53:43 2007 " "Info: Processing started: Wed May 16 16:53:43 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off ram_256 -c ram_256 " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off ram_256 -c ram_256" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISIM_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" {  } {  } 0 0 "Overwriting simulation input file with simulation results" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|ram_256\|sram\[0\]\[1\] 20.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 20.0 ns on register \"\|ram_256\|sram\[0\]\[1\]\"" {  } {  } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|ram_256\|sram\[0\]\[0\] 20.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 20.0 ns on register \"\|ram_256\|sram\[0\]\[0\]\"" {  } {  } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|ram_256\|sram\[0\]\[2\] 40.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 40.0 ns on register \"\|ram_256\|sram\[0\]\[2\]\"" {  } {  } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|ram_256\|sram\[0\]\[3\] 80.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 80.0 ns on register \"\|ram_256\|sram\[0\]\[3\]\"" {  } {  } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|ram_256\|sram\[0\]\[4\] 160.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 160.0 ns on register \"\|ram_256\|sram\[0\]\[4\]\"" {  } {  } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|ram_256\|sram\[0\]\[5\] 320.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 320.0 ns on register \"\|ram_256\|sram\[0\]\[5\]\"" {  } {  } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|ram_256\|sram\[0\]\[6\] 640.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 640.0 ns on register \"\|ram_256\|sram\[0\]\[6\]\"" {  } {  } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|ram_256\|sram\[0\]\[7\] 640.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 640.0 ns on register \"\|ram_256\|sram\[0\]\[7\]\"" {  } {  } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     89.13 % " "Info: Simulation coverage is      89.13 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "3770 " "Info: Number of transitions in simulation is 3770" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 8 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 16 16:53:44 2007 " "Info: Processing ended: Wed May 16 16:53:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}