ram_256.fit.qmsg

在Quartus中实现256的RAM

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 10:55:51 2007 " "Info: Processing started: Thu May 31 10:55:51 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ram_256 -c ram_256 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ram_256 -c ram_256" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ram_256 EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"ram_256\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "27 27 " "Info: No exact pin location assignment(s) for 27 pins of 27 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adr\[1\] " "Info: Pin adr\[1\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "adr\[1\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { adr[1] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { adr[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adr\[2\] " "Info: Pin adr\[2\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "adr\[2\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { adr[2] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { adr[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adr\[3\] " "Info: Pin adr\[3\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "adr\[3\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { adr[3] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { adr[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adr\[4\] " "Info: Pin adr\[4\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "adr\[4\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { adr[4] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { adr[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adr\[5\] " "Info: Pin adr\[5\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "adr\[5\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { adr[5] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { adr[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adr\[6\] " "Info: Pin adr\[6\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "adr\[6\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { adr[6] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { adr[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adr\[7\] " "Info: Pin adr\[7\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "adr\[7\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { adr[7] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { adr[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[0\] " "Info: Pin data_out\[0\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_out\[0\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_out[0] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[1\] " "Info: Pin data_out\[1\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_out\[1\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_out[1] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[2\] " "Info: Pin data_out\[2\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_out\[2\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_out[2] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[3\] " "Info: Pin data_out\[3\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_out\[3\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_out[3] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[4\] " "Info: Pin data_out\[4\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_out\[4\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_out[4] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_out[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[5\] " "Info: Pin data_out\[5\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_out\[5\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_out[5] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_out[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[6\] " "Info: Pin data_out\[6\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_out\[6\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_out[6] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_out[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_out\[7\] " "Info: Pin data_out\[7\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_out\[7\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_out[7] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_out[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "cs " "Info: Pin cs not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "cs" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { cs } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { cs } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "oe " "Info: Pin oe not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "oe" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { oe } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { oe } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[0\] " "Info: Pin data_in\[0\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_in\[0\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_in[0] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_in[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "we " "Info: Pin we not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "we" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { we } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { we } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "adr\[0\] " "Info: Pin adr\[0\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "adr\[0\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { adr[0] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { adr[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[1\] " "Info: Pin data_in\[1\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_in\[1\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_in[1] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_in[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[2\] " "Info: Pin data_in\[2\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_in\[2\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_in[2] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_in[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[3\] " "Info: Pin data_in\[3\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_in\[3\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_in[3] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_in[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[4\] " "Info: Pin data_in\[4\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_in\[4\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_in[4] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_in[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[5\] " "Info: Pin data_in\[5\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_in\[5\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_in[5] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_in[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[6\] " "Info: Pin data_in\[6\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_in\[6\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_in[6] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_in[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "data_in\[7\] " "Info: Pin data_in\[7\] not assigned to an exact location on the device" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "data_in\[7\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "ram_256" "UNKNOWN" "V1" "D:/fpga例子/ram_256/db/ram_256.quartus_db" { Floorplan "D:/fpga例子/ram_256/" "" "" { data_in[7] } "NODE_NAME" } "" } } { "D:/fpga例子/ram_256/ram_256.fld" "" { Floorplan "D:/fpga例子/ram_256/ram_256.fld" "" "" { data_in[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "we Global clock in PIN 17 " "Info: Automatically promoted some destinations of signal \"we\" to use Global clock in PIN 17" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sram\[0\]\[0\]~45 " "Info: Destination \"sram\[0\]\[0\]~45\" may be non-global or may not use global clock" {  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 27 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "ram_256.vhd" "" { Text "D:/fpga例子/ram_256/ram_256.vhd" 9 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}