ram_256.tan.rpt

在Quartus中实现256的RAM

; N/A   ; None         ; 6.683 ns   ; sram[0][2] ; data_out[2] ; we         ;
; N/A   ; None         ; 6.673 ns   ; sram[0][7] ; data_out[7] ; we         ;
; N/A   ; None         ; 6.359 ns   ; sram[0][1] ; data_out[1] ; we         ;
; N/A   ; None         ; 6.356 ns   ; sram[0][6] ; data_out[6] ; we         ;
; N/A   ; None         ; 6.356 ns   ; sram[0][0] ; data_out[0] ; we         ;
+-------+--------------+------------+------------+-------------+------------+


+------------------------------------------------------------------+
; tpd                                                              ;
+-------+-------------------+-----------------+------+-------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To          ;
+-------+-------------------+-----------------+------+-------------+
; N/A   ; None              ; 11.661 ns       ; cs   ; data_out[5] ;
; N/A   ; None              ; 11.661 ns       ; cs   ; data_out[3] ;
; N/A   ; None              ; 11.652 ns       ; cs   ; data_out[7] ;
; N/A   ; None              ; 11.652 ns       ; cs   ; data_out[1] ;
; N/A   ; None              ; 11.651 ns       ; cs   ; data_out[4] ;
; N/A   ; None              ; 11.651 ns       ; cs   ; data_out[2] ;
; N/A   ; None              ; 11.633 ns       ; cs   ; data_out[0] ;
; N/A   ; None              ; 11.313 ns       ; cs   ; data_out[6] ;
; N/A   ; None              ; 11.073 ns       ; oe   ; data_out[5] ;
; N/A   ; None              ; 11.073 ns       ; oe   ; data_out[3] ;
; N/A   ; None              ; 11.064 ns       ; oe   ; data_out[7] ;
; N/A   ; None              ; 11.064 ns       ; oe   ; data_out[1] ;
; N/A   ; None              ; 11.063 ns       ; oe   ; data_out[4] ;
; N/A   ; None              ; 11.063 ns       ; oe   ; data_out[2] ;
; N/A   ; None              ; 11.045 ns       ; oe   ; data_out[0] ;
; N/A   ; None              ; 10.725 ns       ; oe   ; data_out[6] ;
+-------+-------------------+-----------------+------+-------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+------------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To         ; To Clock ;
+---------------+-------------+-----------+------------+------------+----------+
; N/A           ; None        ; -1.728 ns ; we         ; sram[0][0] ; we       ;
; N/A           ; None        ; -1.728 ns ; we         ; sram[0][1] ; we       ;
; N/A           ; None        ; -1.728 ns ; we         ; sram[0][2] ; we       ;
; N/A           ; None        ; -1.728 ns ; we         ; sram[0][3] ; we       ;
; N/A           ; None        ; -1.728 ns ; we         ; sram[0][4] ; we       ;
; N/A           ; None        ; -1.728 ns ; we         ; sram[0][5] ; we       ;
; N/A           ; None        ; -1.728 ns ; we         ; sram[0][6] ; we       ;
; N/A           ; None        ; -1.728 ns ; we         ; sram[0][7] ; we       ;
; N/A           ; None        ; -2.179 ns ; data_in[2] ; sram[0][2] ; we       ;
; N/A           ; None        ; -2.227 ns ; data_in[1] ; sram[0][1] ; we       ;
; N/A           ; None        ; -3.866 ns ; data_in[6] ; sram[0][6] ; we       ;
; N/A           ; None        ; -4.145 ns ; data_in[0] ; sram[0][0] ; we       ;
; N/A           ; None        ; -4.169 ns ; data_in[5] ; sram[0][5] ; we       ;
; N/A           ; None        ; -4.352 ns ; data_in[7] ; sram[0][7] ; we       ;
; N/A           ; None        ; -4.375 ns ; data_in[4] ; sram[0][4] ; we       ;
; N/A           ; None        ; -4.491 ns ; data_in[3] ; sram[0][3] ; we       ;
; N/A           ; None        ; -5.828 ns ; adr[0]     ; sram[0][0] ; we       ;
; N/A           ; None        ; -5.828 ns ; adr[0]     ; sram[0][1] ; we       ;
; N/A           ; None        ; -5.828 ns ; adr[0]     ; sram[0][2] ; we       ;
; N/A           ; None        ; -5.828 ns ; adr[0]     ; sram[0][3] ; we       ;
; N/A           ; None        ; -5.828 ns ; adr[0]     ; sram[0][4] ; we       ;
; N/A           ; None        ; -5.828 ns ; adr[0]     ; sram[0][5] ; we       ;
; N/A           ; None        ; -5.828 ns ; adr[0]     ; sram[0][6] ; we       ;
; N/A           ; None        ; -5.828 ns ; adr[0]     ; sram[0][7] ; we       ;
; N/A           ; None        ; -6.411 ns ; cs         ; sram[0][0] ; we       ;
; N/A           ; None        ; -6.411 ns ; cs         ; sram[0][1] ; we       ;
; N/A           ; None        ; -6.411 ns ; cs         ; sram[0][2] ; we       ;
; N/A           ; None        ; -6.411 ns ; cs         ; sram[0][3] ; we       ;
; N/A           ; None        ; -6.411 ns ; cs         ; sram[0][4] ; we       ;
; N/A           ; None        ; -6.411 ns ; cs         ; sram[0][5] ; we       ;
; N/A           ; None        ; -6.411 ns ; cs         ; sram[0][6] ; we       ;
; N/A           ; None        ; -6.411 ns ; cs         ; sram[0][7] ; we       ;
+---------------+-------------+-----------+------------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu May 31 10:55:56 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ram_256 -c ram_256 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "we" is an undefined clock
Info: No valid register-to-register data paths exist for clock "we"
Info: tsu for register "sram[0][0]" (data pin = "cs", clock pin = "we") is 6.463 ns
    Info: + Longest pin to register delay is 9.159 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_139; Fanout = 2; PIN Node = 'cs'
        Info: 2: + IC(6.070 ns) + CELL(0.292 ns) = 7.837 ns; Loc. = LC_X6_Y1_N2; Fanout = 8; COMB Node = 'sram[0][0]~45'
        Info: 3: + IC(0.455 ns) + CELL(0.867 ns) = 9.159 ns; Loc. = LC_X6_Y1_N3; Fanout = 1; REG Node = 'sram[0][0]'
        Info: Total cell delay = 2.634 ns ( 28.76 % )
        Info: Total interconnect delay = 6.525 ns ( 71.24 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "we" to destination register is 2.733 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'we'
        Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X6_Y1_N3; Fanout = 1; REG Node = 'sram[0][0]'
        Info: Total cell delay = 2.180 ns ( 79.77 % )
        Info: Total interconnect delay = 0.553 ns ( 20.23 % )
Info: tco from clock "we" to destination pin "data_out[4]" through register "sram[0][4]" is 6.687 ns
    Info: + Longest clock path from clock "we" to source register is 2.733 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'we'
        Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X6_Y1_N6; Fanout = 1; REG Node = 'sram[0][4]'
        Info: Total cell delay = 2.180 ns ( 79.77 % )
        Info: Total interconnect delay = 0.553 ns ( 20.23 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.730 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N6; Fanout = 1; REG Node = 'sram[0][4]'
        Info: 2: + IC(1.622 ns) + CELL(2.108 ns) = 3.730 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'data_out[4]'
        Info: Total cell delay = 2.108 ns ( 56.51 % )
        Info: Total interconnect delay = 1.622 ns ( 43.49 % )
Info: Longest tpd from source pin "cs" to destination pin "data_out[5]" is 11.661 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_139; Fanout = 2; PIN Node = 'cs'
    Info: 2: + IC(6.072 ns) + CELL(0.292 ns) = 7.839 ns; Loc. = LC_X6_Y1_N0; Fanout = 8; COMB Node = 'process1~0'
    Info: 3: + IC(1.743 ns) + CELL(2.079 ns) = 11.661 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'data_out[5]'
    Info: Total cell delay = 3.846 ns ( 32.98 % )
    Info: Total interconnect delay = 7.815 ns ( 67.02 % )
Info: th for register "sram[0][0]" (data pin = "we", clock pin = "we") is -1.728 ns
    Info: + Longest clock path from clock "we" to destination register is 2.733 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'we'
        Info: 2: + IC(0.553 ns) + CELL(0.711 ns) = 2.733 ns; Loc. = LC_X6_Y1_N3; Fanout = 1; REG Node = 'sram[0][0]'
        Info: Total cell delay = 2.180 ns ( 79.77 % )
        Info: Total interconnect delay = 0.553 ns ( 20.23 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 4.476 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'we'
        Info: 2: + IC(1.095 ns) + CELL(0.590 ns) = 3.154 ns; Loc. = LC_X6_Y1_N2; Fanout = 8; COMB Node = 'sram[0][0]~45'
        Info: 3: + IC(0.455 ns) + CELL(0.867 ns) = 4.476 ns; Loc. = LC_X6_Y1_N3; Fanout = 1; REG Node = 'sram[0][0]'
        Info: Total cell delay = 2.926 ns ( 65.37 % )
        Info: Total interconnect delay = 1.550 ns ( 34.63 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 31 10:55:57 2007
    Info: Elapsed time: 00:00:01