sine_generator.tan.qmsg

在quartus 11 5.1 里用VHDL编写的正弦波发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register generator_acc6:U4\|REG_Q\[3\] register generator_reg8:U7\|TEMP_Q_1\[4\] 203.09 MHz 4.924 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 203.09 MHz between source register \"generator_acc6:U4\|REG_Q\[3\]\" and destination register \"generator_reg8:U7\|TEMP_Q_1\[4\]\" (period= 4.924 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.768 ns + Longest register register " "Info: + Longest register to register delay is 4.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns generator_acc6:U4\|REG_Q\[3\] 1 REG LC_X44_Y11_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y11_N4; Fanout = 4; REG Node = 'generator_acc6:U4\|REG_Q\[3\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { generator_acc6:U4|REG_Q[3] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.524 ns) 1.316 ns generator_adder:U3\|add~137 2 COMB LC_X45_Y11_N4 2 " "Info: 2: + IC(0.792 ns) + CELL(0.524 ns) = 1.316 ns; Loc. = LC_X45_Y11_N4; Fanout = 2; COMB Node = 'generator_adder:U3\|add~137'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "1.316 ns" { generator_acc6:U4|REG_Q[3] generator_adder:U3|add~137 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 1.765 ns generator_adder:U3\|add~120 3 COMB LC_X45_Y11_N6 24 " "Info: 3: + IC(0.000 ns) + CELL(0.449 ns) = 1.765 ns; Loc. = LC_X45_Y11_N6; Fanout = 24; COMB Node = 'generator_adder:U3\|add~120'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "0.449 ns" { generator_adder:U3|add~137 generator_adder:U3|add~120 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.366 ns) 3.215 ns generator_sin:U6\|Mux~1326 4 COMB LC_X45_Y12_N7 1 " "Info: 4: + IC(1.084 ns) + CELL(0.366 ns) = 3.215 ns; Loc. = LC_X45_Y12_N7; Fanout = 1; COMB Node = 'generator_sin:U6\|Mux~1326'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "1.450 ns" { generator_adder:U3|add~120 generator_sin:U6|Mux~1326 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(0.366 ns) 3.903 ns generator_sin:U6\|Mux~1327 5 COMB LC_X45_Y12_N2 1 " "Info: 5: + IC(0.322 ns) + CELL(0.366 ns) = 3.903 ns; Loc. = LC_X45_Y12_N2; Fanout = 1; COMB Node = 'generator_sin:U6\|Mux~1327'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "0.688 ns" { generator_sin:U6|Mux~1326 generator_sin:U6|Mux~1327 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.539 ns) 4.768 ns generator_reg8:U7\|TEMP_Q_1\[4\] 6 REG LC_X45_Y12_N4 1 " "Info: 6: + IC(0.326 ns) + CELL(0.539 ns) = 4.768 ns; Loc. = LC_X45_Y12_N4; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[4\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "0.865 ns" { generator_sin:U6|Mux~1327 generator_reg8:U7|TEMP_Q_1[4] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 355 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.244 ns ( 47.06 % ) " "Info: Total cell delay = 2.244 ns ( 47.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.524 ns ( 52.94 % ) " "Info: Total interconnect delay = 2.524 ns ( 52.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "4.768 ns" { generator_acc6:U4|REG_Q[3] generator_adder:U3|add~137 generator_adder:U3|add~120 generator_sin:U6|Mux~1326 generator_sin:U6|Mux~1327 generator_reg8:U7|TEMP_Q_1[4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.768 ns" { generator_acc6:U4|REG_Q[3] generator_adder:U3|add~137 generator_adder:U3|add~120 generator_sin:U6|Mux~1326 generator_sin:U6|Mux~1327 generator_reg8:U7|TEMP_Q_1[4] } { 0.000ns 0.792ns 0.000ns 1.084ns 0.322ns 0.326ns } { 0.000ns 0.524ns 0.449ns 0.366ns 0.366ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.010 ns - Smallest " "Info: - Smallest clock skew is 0.010 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.872 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 26 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { CLK } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(0.542 ns) 2.872 ns generator_reg8:U7\|TEMP_Q_1\[4\] 2 REG LC_X45_Y12_N4 1 " "Info: 2: + IC(1.605 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X45_Y12_N4; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[4\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.147 ns" { CLK generator_reg8:U7|TEMP_Q_1[4] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 355 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.12 % ) " "Info: Total cell delay = 1.267 ns ( 44.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.605 ns ( 55.88 % ) " "Info: Total interconnect delay = 1.605 ns ( 55.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.872 ns" { CLK generator_reg8:U7|TEMP_Q_1[4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.872 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[4] } { 0.000ns 0.000ns 1.605ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.862 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 26 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { CLK } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.595 ns) + CELL(0.542 ns) 2.862 ns generator_acc6:U4\|REG_Q\[3\] 2 REG LC_X44_Y11_N4 4 " "Info: 2: + IC(1.595 ns) + CELL(0.542 ns) = 2.862 ns; Loc. = LC_X44_Y11_N4; Fanout = 4; REG Node = 'generator_acc6:U4\|REG_Q\[3\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.137 ns" { CLK generator_acc6:U4|REG_Q[3] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.27 % ) " "Info: Total cell delay = 1.267 ns ( 44.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.595 ns ( 55.73 % ) " "Info: Total interconnect delay = 1.595 ns ( 55.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.862 ns" { CLK generator_acc6:U4|REG_Q[3] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.862 ns" { CLK CLK~out0 generator_acc6:U4|REG_Q[3] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.872 ns" { CLK generator_reg8:U7|TEMP_Q_1[4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.872 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[4] } { 0.000ns 0.000ns 1.605ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.862 ns" { CLK generator_acc6:U4|REG_Q[3] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.862 ns" { CLK CLK~out0 generator_acc6:U4|REG_Q[3] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 355 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "4.768 ns" { generator_acc6:U4|REG_Q[3] generator_adder:U3|add~137 generator_adder:U3|add~120 generator_sin:U6|Mux~1326 generator_sin:U6|Mux~1327 generator_reg8:U7|TEMP_Q_1[4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.768 ns" { generator_acc6:U4|REG_Q[3] generator_adder:U3|add~137 generator_adder:U3|add~120 generator_sin:U6|Mux~1326 generator_sin:U6|Mux~1327 generator_reg8:U7|TEMP_Q_1[4] } { 0.000ns 0.792ns 0.000ns 1.084ns 0.322ns 0.326ns } { 0.000ns 0.524ns 0.449ns 0.366ns 0.366ns 0.539ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.872 ns" { CLK generator_reg8:U7|TEMP_Q_1[4] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.872 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[4] } { 0.000ns 0.000ns 1.605ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.862 ns" { CLK generator_acc6:U4|REG_Q[3] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.862 ns" { CLK CLK~out0 generator_acc6:U4|REG_Q[3] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "generator_reg6:U2\|TEMP_Q_0\[3\] CE CLK 4.423 ns register " "Info: tsu for register \"generator_reg6:U2\|TEMP_Q_0\[3\]\" (data pin = \"CE\", clock pin = \"CLK\") is 4.423 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.275 ns + Longest pin register " "Info: + Longest pin to register delay is 7.275 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns CE 1 PIN PIN_W7 16 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W7; Fanout = 16; PIN Node = 'CE'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { CE } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 386 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.442 ns) + CELL(0.280 ns) 5.809 ns generator_and2:U8\|O 2 COMB LC_X46_Y11_N3 6 " "Info: 2: + IC(4.442 ns) + CELL(0.280 ns) = 5.809 ns; Loc. = LC_X46_Y11_N3; Fanout = 6; COMB Node = 'generator_and2:U8\|O'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "4.722 ns" { CE generator_and2:U8|O } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.761 ns) + CELL(0.705 ns) 7.275 ns generator_reg6:U2\|TEMP_Q_0\[3\] 3 REG LC_X44_Y11_N0 2 " "Info: 3: + IC(0.761 ns) + CELL(0.705 ns) = 7.275 ns; Loc. = LC_X44_Y11_N0; Fanout = 2; REG Node = 'generator_reg6:U2\|TEMP_Q_0\[3\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "1.466 ns" { generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[3] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 307 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.072 ns ( 28.48 % ) " "Info: Total cell delay = 2.072 ns ( 28.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.203 ns ( 71.52 % ) " "Info: Total interconnect delay = 5.203 ns ( 71.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "7.275 ns" { CE generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[3] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "7.275 ns" { CE CE~out0 generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[3] } { 0.000ns 0.000ns 4.442ns 0.761ns } { 0.000ns 1.087ns 0.280ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 307 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.862 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 26 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { CLK } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.595 ns) + CELL(0.542 ns) 2.862 ns generator_reg6:U2\|TEMP_Q_0\[3\] 2 REG LC_X44_Y11_N0 2 " "Info: 2: + IC(1.595 ns) + CELL(0.542 ns) = 2.862 ns; Loc. = LC_X44_Y11_N0; Fanout = 2; REG Node = 'generator_reg6:U2\|TEMP_Q_0\[3\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.137 ns" { CLK generator_reg6:U2|TEMP_Q_0[3] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 307 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.27 % ) " "Info: Total cell delay = 1.267 ns ( 44.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.595 ns ( 55.73 % ) " "Info: Total interconnect delay = 1.595 ns ( 55.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.862 ns" { CLK generator_reg6:U2|TEMP_Q_0[3] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.862 ns" { CLK CLK~out0 generator_reg6:U2|TEMP_Q_0[3] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "7.275 ns" { CE generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[3] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "7.275 ns" { CE CE~out0 generator_and2:U8|O generator_reg6:U2|TEMP_Q_0[3] } { 0.000ns 0.000ns 4.442ns 0.761ns } { 0.000ns 1.087ns 0.280ns 0.705ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.862 ns" { CLK generator_reg6:U2|TEMP_Q_0[3] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.862 ns" { CLK CLK~out0 generator_reg6:U2|TEMP_Q_0[3] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[6\] generator_reg8:U7\|TEMP_Q_1\[6\] 7.531 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[6\]\" through register \"generator_reg8:U7\|TEMP_Q_1\[6\]\" is 7.531 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.872 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 26 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { CLK } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(0.542 ns) 2.872 ns generator_reg8:U7\|TEMP_Q_1\[6\] 2 REG LC_X46_Y12_N3 1 " "Info: 2: + IC(1.605 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X46_Y12_N3; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[6\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.147 ns" { CLK generator_reg8:U7|TEMP_Q_1[6] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 355 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.12 % ) " "Info: Total cell delay = 1.267 ns ( 44.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.605 ns ( 55.88 % ) " "Info: Total interconnect delay = 1.605 ns ( 55.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.872 ns" { CLK generator_reg8:U7|TEMP_Q_1[6] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.872 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[6] } { 0.000ns 0.000ns 1.605ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 355 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.503 ns + Longest register pin " "Info: + Longest register to pin delay is 4.503 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns generator_reg8:U7\|TEMP_Q_1\[6\] 1 REG LC_X46_Y12_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X46_Y12_N3; Fanout = 1; REG Node = 'generator_reg8:U7\|TEMP_Q_1\[6\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { generator_reg8:U7|TEMP_Q_1[6] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 355 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.099 ns) + CELL(2.404 ns) 4.503 ns Q\[6\] 2 PIN PIN_V5 0 " "Info: 2: + IC(2.099 ns) + CELL(2.404 ns) = 4.503 ns; Loc. = PIN_V5; Fanout = 0; PIN Node = 'Q\[6\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "4.503 ns" { generator_reg8:U7|TEMP_Q_1[6] Q[6] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 387 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 53.39 % ) " "Info: Total cell delay = 2.404 ns ( 53.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.099 ns ( 46.61 % ) " "Info: Total interconnect delay = 2.099 ns ( 46.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "4.503 ns" { generator_reg8:U7|TEMP_Q_1[6] Q[6] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.503 ns" { generator_reg8:U7|TEMP_Q_1[6] Q[6] } { 0.000ns 2.099ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.872 ns" { CLK generator_reg8:U7|TEMP_Q_1[6] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.872 ns" { CLK CLK~out0 generator_reg8:U7|TEMP_Q_1[6] } { 0.000ns 0.000ns 1.605ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "4.503 ns" { generator_reg8:U7|TEMP_Q_1[6] Q[6] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.503 ns" { generator_reg8:U7|TEMP_Q_1[6] Q[6] } { 0.000ns 2.099ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "generator_reg6:U1\|TEMP_Q_0\[2\] DATA\[2\] CLK -1.886 ns register " "Info: th for register \"generator_reg6:U1\|TEMP_Q_0\[2\]\" (data pin = \"DATA\[2\]\", clock pin = \"CLK\") is -1.886 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.862 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 26 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 26; CLK Node = 'CLK'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { CLK } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 388 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.595 ns) + CELL(0.542 ns) 2.862 ns generator_reg6:U1\|TEMP_Q_0\[2\] 2 REG LC_X46_Y11_N4 3 " "Info: 2: + IC(1.595 ns) + CELL(0.542 ns) = 2.862 ns; Loc. = LC_X46_Y11_N4; Fanout = 3; REG Node = 'generator_reg6:U1\|TEMP_Q_0\[2\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.137 ns" { CLK generator_reg6:U1|TEMP_Q_0[2] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 307 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.27 % ) " "Info: Total cell delay = 1.267 ns ( 44.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.595 ns ( 55.73 % ) " "Info: Total interconnect delay = 1.595 ns ( 55.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.862 ns" { CLK generator_reg6:U1|TEMP_Q_0[2] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.862 ns" { CLK CLK~out0 generator_reg6:U1|TEMP_Q_0[2] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 307 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.848 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns DATA\[2\] 1 PIN PIN_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_N3; Fanout = 2; PIN Node = 'DATA\[2\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "" { DATA[2] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 382 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.529 ns) + CELL(0.085 ns) 4.848 ns generator_reg6:U1\|TEMP_Q_0\[2\] 2 REG LC_X46_Y11_N4 3 " "Info: 2: + IC(3.529 ns) + CELL(0.085 ns) = 4.848 ns; Loc. = LC_X46_Y11_N4; Fanout = 3; REG Node = 'generator_reg6:U1\|TEMP_Q_0\[2\]'" {  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "3.614 ns" { DATA[2] generator_reg6:U1|TEMP_Q_0[2] } "NODE_NAME" } "" } } { "sine_generator.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/903812sine_generator/sine_generator.vhd" 307 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 27.21 % ) " "Info: Total cell delay = 1.319 ns ( 27.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.529 ns ( 72.79 % ) " "Info: Total interconnect delay = 3.529 ns ( 72.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "4.848 ns" { DATA[2] generator_reg6:U1|TEMP_Q_0[2] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.848 ns" { DATA[2] DATA[2]~out0 generator_reg6:U1|TEMP_Q_0[2] } { 0.000ns 0.000ns 3.529ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "2.862 ns" { CLK generator_reg6:U1|TEMP_Q_0[2] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "2.862 ns" { CLK CLK~out0 generator_reg6:U1|TEMP_Q_0[2] } { 0.000ns 0.000ns 1.595ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "sine_generator" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/903812sine_generator/db/sine_generator.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/903812sine_generator/" "" "4.848 ns" { DATA[2] generator_reg6:U1|TEMP_Q_0[2] } "NODE_NAME" } "" } } { "d:/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/bin/Technology_Viewer.qrui" "4.848 ns" { DATA[2] DATA[2]~out0 generator_reg6:U1|TEMP_Q_0[2] } { 0.000ns 0.000ns 3.529ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}