sine_generator.hier_info

在quartus 11 5.1 里用VHDL编写的正弦波发生器

|sine_generator
DATA[0] => generator_reg6:U2.DATA[0]
DATA[0] => generator_reg6:U1.DATA[0]
DATA[1] => generator_reg6:U2.DATA[1]
DATA[1] => generator_reg6:U1.DATA[1]
DATA[2] => generator_reg6:U2.DATA[2]
DATA[2] => generator_reg6:U1.DATA[2]
DATA[3] => generator_reg6:U2.DATA[3]
DATA[3] => generator_reg6:U1.DATA[3]
DATA[4] => generator_reg6:U2.DATA[4]
DATA[4] => generator_reg6:U1.DATA[4]
DATA[5] => generator_reg6:U2.DATA[5]
DATA[5] => generator_reg6:U1.DATA[5]
PR => generator_and2:U9.I1
FR => generator_and2:U8.I1
CLR => generator_reg8:U7.CLR
CLR => generator_acc6:U4.CLR
CLR => generator_reg6:U2.CLR
CLR => generator_reg6:U1.CLR
CE => generator_and2:U9.I0
CE => generator_and2:U8.I0
CE => generator_reg8:U7.CE
CE => generator_acc6:U4.CE
Q[0] <= generator_reg8:U7.Q[0]
Q[1] <= generator_reg8:U7.Q[1]
Q[2] <= generator_reg8:U7.Q[2]
Q[3] <= generator_reg8:U7.Q[3]
Q[4] <= generator_reg8:U7.Q[4]
Q[5] <= generator_reg8:U7.Q[5]
Q[6] <= generator_reg8:U7.Q[6]
Q[7] <= generator_reg8:U7.Q[7]
CLK => generator_reg8:U7.CLK
CLK => generator_acc6:U4.CLK
CLK => generator_reg6:U2.CLK
CLK => generator_reg6:U1.CLK


|sine_generator|generator_reg6:U1
CLR => TEMP_Q_0[4].ACLR
CLR => TEMP_Q_0[3].ACLR
CLR => TEMP_Q_0[2].ACLR
CLR => TEMP_Q_0[1].ACLR
CLR => TEMP_Q_0[0].ACLR
CLR => TEMP_Q_0[5].ACLR
CE => TEMP_Q_0[4].ENA
CE => TEMP_Q_0[3].ENA
CE => TEMP_Q_0[2].ENA
CE => TEMP_Q_0[1].ENA
CE => TEMP_Q_0[0].ENA
CE => TEMP_Q_0[5].ENA
CLK => TEMP_Q_0[4].CLK
CLK => TEMP_Q_0[3].CLK
CLK => TEMP_Q_0[2].CLK
CLK => TEMP_Q_0[1].CLK
CLK => TEMP_Q_0[0].CLK
CLK => TEMP_Q_0[5].CLK
DATA[0] => TEMP_Q_0[0].DATAIN
DATA[1] => TEMP_Q_0[1].DATAIN
DATA[2] => TEMP_Q_0[2].DATAIN
DATA[3] => TEMP_Q_0[3].DATAIN
DATA[4] => TEMP_Q_0[4].DATAIN
DATA[5] => TEMP_Q_0[5].DATAIN
Q[0] <= TEMP_Q_0[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_0[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_0[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_0[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_0[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_0[5].DB_MAX_OUTPUT_PORT_TYPE


|sine_generator|generator_sin:U6
OE => process0~0.OE
OE => process0~1.OE
OE => process0~2.OE
OE => process0~3.OE
OE => process0~4.OE
OE => process0~5.OE
OE => process0~6.OE
OE => process0~7.OE
ADDRESS[0] => Mux~0.IN69
ADDRESS[0] => Mux~1.IN69
ADDRESS[0] => Mux~2.IN69
ADDRESS[0] => Mux~3.IN69
ADDRESS[0] => Mux~4.IN69
ADDRESS[0] => Mux~5.IN69
ADDRESS[0] => Mux~6.IN69
ADDRESS[0] => Mux~7.IN69
ADDRESS[1] => Mux~0.IN68
ADDRESS[1] => Mux~1.IN68
ADDRESS[1] => Mux~2.IN68
ADDRESS[1] => Mux~3.IN68
ADDRESS[1] => Mux~4.IN68
ADDRESS[1] => Mux~5.IN68
ADDRESS[1] => Mux~6.IN68
ADDRESS[1] => Mux~7.IN68
ADDRESS[2] => Mux~0.IN67
ADDRESS[2] => Mux~1.IN67
ADDRESS[2] => Mux~2.IN67
ADDRESS[2] => Mux~3.IN67
ADDRESS[2] => Mux~4.IN67
ADDRESS[2] => Mux~5.IN67
ADDRESS[2] => Mux~6.IN67
ADDRESS[2] => Mux~7.IN67
ADDRESS[3] => Mux~0.IN66
ADDRESS[3] => Mux~1.IN66
ADDRESS[3] => Mux~2.IN66
ADDRESS[3] => Mux~3.IN66
ADDRESS[3] => Mux~4.IN66
ADDRESS[3] => Mux~5.IN66
ADDRESS[3] => Mux~6.IN66
ADDRESS[3] => Mux~7.IN66
ADDRESS[4] => Mux~0.IN65
ADDRESS[4] => Mux~1.IN65
ADDRESS[4] => Mux~2.IN65
ADDRESS[4] => Mux~3.IN65
ADDRESS[4] => Mux~4.IN65
ADDRESS[4] => Mux~5.IN65
ADDRESS[4] => Mux~6.IN65
ADDRESS[4] => Mux~7.IN65
ADDRESS[5] => Mux~0.IN64
ADDRESS[5] => Mux~1.IN64
ADDRESS[5] => Mux~2.IN64
ADDRESS[5] => Mux~3.IN64
ADDRESS[5] => Mux~4.IN64
ADDRESS[5] => Mux~5.IN64
ADDRESS[5] => Mux~6.IN64
ADDRESS[5] => Mux~7.IN64
Q[0] <= process0~7.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= process0~6.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= process0~5.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= process0~4.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= process0~3.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= process0~2.DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= process0~1.DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= process0~0.DB_MAX_OUTPUT_PORT_TYPE


|sine_generator|generator_reg6:U2
CLR => TEMP_Q_0[4].ACLR
CLR => TEMP_Q_0[3].ACLR
CLR => TEMP_Q_0[2].ACLR
CLR => TEMP_Q_0[1].ACLR
CLR => TEMP_Q_0[0].ACLR
CLR => TEMP_Q_0[5].ACLR
CE => TEMP_Q_0[4].ENA
CE => TEMP_Q_0[3].ENA
CE => TEMP_Q_0[2].ENA
CE => TEMP_Q_0[1].ENA
CE => TEMP_Q_0[0].ENA
CE => TEMP_Q_0[5].ENA
CLK => TEMP_Q_0[4].CLK
CLK => TEMP_Q_0[3].CLK
CLK => TEMP_Q_0[2].CLK
CLK => TEMP_Q_0[1].CLK
CLK => TEMP_Q_0[0].CLK
CLK => TEMP_Q_0[5].CLK
DATA[0] => TEMP_Q_0[0].DATAIN
DATA[1] => TEMP_Q_0[1].DATAIN
DATA[2] => TEMP_Q_0[2].DATAIN
DATA[3] => TEMP_Q_0[3].DATAIN
DATA[4] => TEMP_Q_0[4].DATAIN
DATA[5] => TEMP_Q_0[5].DATAIN
Q[0] <= TEMP_Q_0[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_0[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_0[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_0[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_0[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_0[5].DB_MAX_OUTPUT_PORT_TYPE


|sine_generator|generator_adder:U3
A[0] => add~0.IN6
A[1] => add~0.IN5
A[2] => add~0.IN4
A[3] => add~0.IN3
A[4] => add~0.IN2
A[5] => add~0.IN1
B[0] => add~0.IN12
B[1] => add~0.IN11
B[2] => add~0.IN10
B[3] => add~0.IN9
B[4] => add~0.IN8
B[5] => add~0.IN7
Q[0] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= add~0.DB_MAX_OUTPUT_PORT_TYPE


|sine_generator|generator_acc6:U4
CLK => REG_Q[4].CLK
CLK => REG_Q[3].CLK
CLK => REG_Q[2].CLK
CLK => REG_Q[1].CLK
CLK => REG_Q[0].CLK
CLK => REG_Q[5].CLK
CE => REG_Q[4].ENA
CE => REG_Q[3].ENA
CE => REG_Q[2].ENA
CE => REG_Q[1].ENA
CE => REG_Q[0].ENA
CE => REG_Q[5].ENA
CLR => REG_Q[4].ACLR
CLR => REG_Q[3].ACLR
CLR => REG_Q[2].ACLR
CLR => REG_Q[1].ACLR
CLR => REG_Q[0].ACLR
CLR => REG_Q[5].ACLR
A[0] => add~0.IN6
A[1] => add~0.IN5
A[2] => add~0.IN4
A[3] => add~0.IN3
A[4] => add~0.IN2
A[5] => add~0.IN1
Q[0] <= REG_Q[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= REG_Q[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= REG_Q[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= REG_Q[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= REG_Q[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= REG_Q[5].DB_MAX_OUTPUT_PORT_TYPE


|sine_generator|generator_reg8:U7
CLR => TEMP_Q_1[6].ACLR
CLR => TEMP_Q_1[5].ACLR
CLR => TEMP_Q_1[4].ACLR
CLR => TEMP_Q_1[3].ACLR
CLR => TEMP_Q_1[2].ACLR
CLR => TEMP_Q_1[1].ACLR
CLR => TEMP_Q_1[0].ACLR
CLR => TEMP_Q_1[7].ACLR
CE => TEMP_Q_1[6].ENA
CE => TEMP_Q_1[5].ENA
CE => TEMP_Q_1[4].ENA
CE => TEMP_Q_1[3].ENA
CE => TEMP_Q_1[2].ENA
CE => TEMP_Q_1[1].ENA
CE => TEMP_Q_1[0].ENA
CE => TEMP_Q_1[7].ENA
CLK => TEMP_Q_1[6].CLK
CLK => TEMP_Q_1[5].CLK
CLK => TEMP_Q_1[4].CLK
CLK => TEMP_Q_1[3].CLK
CLK => TEMP_Q_1[2].CLK
CLK => TEMP_Q_1[1].CLK
CLK => TEMP_Q_1[0].CLK
CLK => TEMP_Q_1[7].CLK
DATA[0] => TEMP_Q_1[0].DATAIN
DATA[1] => TEMP_Q_1[1].DATAIN
DATA[2] => TEMP_Q_1[2].DATAIN
DATA[3] => TEMP_Q_1[3].DATAIN
DATA[4] => TEMP_Q_1[4].DATAIN
DATA[5] => TEMP_Q_1[5].DATAIN
DATA[6] => TEMP_Q_1[6].DATAIN
DATA[7] => TEMP_Q_1[7].DATAIN
Q[0] <= TEMP_Q_1[0].DB_MAX_OUTPUT_PORT_TYPE
Q[1] <= TEMP_Q_1[1].DB_MAX_OUTPUT_PORT_TYPE
Q[2] <= TEMP_Q_1[2].DB_MAX_OUTPUT_PORT_TYPE
Q[3] <= TEMP_Q_1[3].DB_MAX_OUTPUT_PORT_TYPE
Q[4] <= TEMP_Q_1[4].DB_MAX_OUTPUT_PORT_TYPE
Q[5] <= TEMP_Q_1[5].DB_MAX_OUTPUT_PORT_TYPE
Q[6] <= TEMP_Q_1[6].DB_MAX_OUTPUT_PORT_TYPE
Q[7] <= TEMP_Q_1[7].DB_MAX_OUTPUT_PORT_TYPE


|sine_generator|generator_and2:U8
I0 => O~0.IN0
I1 => O~0.IN1
O <= O~0.DB_MAX_OUTPUT_PORT_TYPE


|sine_generator|generator_and2:U9
I0 => O~0.IN0
I1 => O~0.IN1
O <= O~0.DB_MAX_OUTPUT_PORT_TYPE