pocpoc.rpt

简单的POC实现与打印机

         #  _LC3_C22 &  _LC3_C34;

-- Node name is '|POC:15|:55' = '|POC:15|BR7' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = DFFE( _EQ008, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ008 =  DATAIN7 & !_LC3_C22
         #  _LC2_C19 &  _LC3_C22;

-- Node name is '|POC:15|:44' = '|POC:15|current_state0' 
-- Equation name is '_LC6_C22', type is buried 
_LC6_C22 = DFFE( _EQ009, GLOBAL( CLOCK), GLOBAL(!RESET),  VCC,  VCC);
  _EQ009 =  _LC4_C19 &  _LC5_C22 &  RW;

-- Node name is '|POC:15|:43' = '|POC:15|current_state1' 
-- Equation name is '_LC4_C22', type is buried 
_LC4_C22 = DFFE(!_LC5_C22, GLOBAL( CLOCK), GLOBAL(!RESET),  VCC,  VCC);

-- Node name is '|POC:15|:54' = '|POC:15|SR0' 
-- Equation name is '_LC7_C22', type is buried 
_LC7_C22 = DFFE( _EQ010, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ010 =  _LC7_C22 & !RW
         # !_LC3_C19 &  _LC7_C22
         #  DATAIN0 &  _LC3_C19 &  RW;

-- Node name is '|POC:15|:53' = '|POC:15|SR1' 
-- Equation name is '_LC2_E29', type is buried 
_LC2_E29 = DFFE( _EQ011, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ011 =  _LC2_E29 & !RW
         #  _LC2_E29 & !_LC3_C19
         #  DATAIN1 &  _LC3_C19 &  RW;

-- Node name is '|POC:15|:52' = '|POC:15|SR2' 
-- Equation name is '_LC1_F29', type is buried 
_LC1_F29 = DFFE( _EQ012, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ012 =  _LC1_F29 & !RW
         #  _LC1_F29 & !_LC3_C19
         #  DATAIN2 &  _LC3_C19 &  RW;

-- Node name is '|POC:15|:51' = '|POC:15|SR3' 
-- Equation name is '_LC2_C34', type is buried 
_LC2_C34 = DFFE( _EQ013, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ013 =  _LC2_C34 & !RW
         #  _LC2_C34 & !_LC3_C19
         #  DATAIN3 &  _LC3_C19 &  RW;

-- Node name is '|POC:15|:50' = '|POC:15|SR4' 
-- Equation name is '_LC4_E29', type is buried 
_LC4_E29 = DFFE( _EQ014, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ014 =  _LC4_E29 & !RW
         # !_LC3_C19 &  _LC4_E29
         #  DATAIN4 &  _LC3_C19 &  RW;

-- Node name is '|POC:15|:49' = '|POC:15|SR5' 
-- Equation name is '_LC2_F29', type is buried 
_LC2_F29 = DFFE( _EQ015, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ015 =  _LC2_F29 & !RW
         #  _LC2_F29 & !_LC3_C19
         #  DATAIN5 &  _LC3_C19 &  RW;

-- Node name is '|POC:15|:48' = '|POC:15|SR6' 
-- Equation name is '_LC4_C34', type is buried 
_LC4_C34 = DFFE( _EQ016, GLOBAL( CLOCK),  VCC,  VCC,  VCC);
  _EQ016 =  _LC4_C34 & !RW
         # !_LC3_C19 &  _LC4_C34
         #  DATAIN6 &  _LC3_C19 &  RW;

-- Node name is '|POC:15|~387~1' 
-- Equation name is '_LC3_C22', type is buried 
-- synthesized logic cell 
_LC3_C22 = LCELL( _EQ017);
  _EQ017 = !_LC5_C22
         # !_LC4_C19
         # !RW
         #  _LC3_C19;

-- Node name is '|POC:15|~591~1' 
-- Equation name is '_LC3_C19', type is buried 
-- synthesized logic cell 
_LC3_C19 = LCELL( _EQ018);
  _EQ018 = !ADDRESS0 & !ADDRESS1 & !ADDRESS2 &  CS;

-- Node name is '|POC:15|~603~1' 
-- Equation name is '_LC4_C19', type is buried 
-- synthesized logic cell 
_LC4_C19 = LCELL( _EQ019);
  _EQ019 =  ADDRESS0 & !ADDRESS1 & !ADDRESS2 &  CS;

-- Node name is '|POC:15|:704' 
-- Equation name is '_LC1_C19', type is buried 
!_LC1_C19 = _LC1_C19~NOT;
_LC1_C19~NOT = LCELL( _EQ020);
  _EQ020 =  _LC3_C19 & !RW
         #  _LC4_C19 & !RW;

-- Node name is '|POC:15|:705' 
-- Equation name is '_LC8_C19', type is buried 
_LC8_C19 = LCELL( _EQ021);
  _EQ021 =  _LC3_C19 &  _LC5_C22 & !RW
         #  _LC5_C19;

-- Node name is '|POC:15|:707' 
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = LCELL( _EQ022);
  _EQ022 =  _LC2_C19 &  _LC4_C19 & !RW;

-- Node name is '|POC:15|:720' 
-- Equation name is '_LC5_C34', type is buried 
_LC5_C34 = LCELL( _EQ023);
  _EQ023 =  _LC3_C19 &  _LC4_C34 & !RW
         #  _LC8_C34;

-- Node name is '|POC:15|:722' 
-- Equation name is '_LC8_C34', type is buried 
_LC8_C34 = LCELL( _EQ024);
  _EQ024 =  _LC3_C34 &  _LC4_C19 & !RW;

-- Node name is '|POC:15|:735' 
-- Equation name is '_LC7_F29', type is buried 
_LC7_F29 = LCELL( _EQ025);
  _EQ025 =  _LC2_F29 &  _LC3_C19 & !RW
         #  _LC8_F29;

-- Node name is '|POC:15|:737' 
-- Equation name is '_LC8_F29', type is buried 
_LC8_F29 = LCELL( _EQ026);
  _EQ026 =  _LC3_F29 &  _LC4_C19 & !RW;

-- Node name is '|POC:15|:750' 
-- Equation name is '_LC7_E29', type is buried 
_LC7_E29 = LCELL( _EQ027);
  _EQ027 =  _LC3_C19 &  _LC4_E29 & !RW
         #  _LC8_E29;

-- Node name is '|POC:15|:752' 
-- Equation name is '_LC8_E29', type is buried 
_LC8_E29 = LCELL( _EQ028);
  _EQ028 =  _LC4_C19 &  _LC5_E29 & !RW;

-- Node name is '|POC:15|:765' 
-- Equation name is '_LC1_C34', type is buried 
_LC1_C34 = LCELL( _EQ029);
  _EQ029 =  _LC2_C34 &  _LC3_C19 & !RW
         #  _LC7_C34;

-- Node name is '|POC:15|:767' 
-- Equation name is '_LC7_C34', type is buried 
_LC7_C34 = LCELL( _EQ030);
  _EQ030 =  _LC4_C19 &  _LC6_C34 & !RW;

-- Node name is '|POC:15|:780' 
-- Equation name is '_LC6_F29', type is buried 
_LC6_F29 = LCELL( _EQ031);
  _EQ031 =  _LC1_F29 &  _LC3_C19 & !RW
         #  _LC4_F29;

-- Node name is '|POC:15|:782' 
-- Equation name is '_LC4_F29', type is buried 
_LC4_F29 = LCELL( _EQ032);
  _EQ032 =  _LC4_C19 &  _LC5_F29 & !RW;

-- Node name is '|POC:15|:795' 
-- Equation name is '_LC3_E29', type is buried 
_LC3_E29 = LCELL( _EQ033);
  _EQ033 =  _LC2_E29 &  _LC3_C19 & !RW
         #  _LC6_E29;

-- Node name is '|POC:15|:797' 
-- Equation name is '_LC6_E29', type is buried 
_LC6_E29 = LCELL( _EQ034);
  _EQ034 =  _LC1_E29 &  _LC4_C19 & !RW;

-- Node name is '|POC:15|:810' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ035);
  _EQ035 =  _LC3_C19 &  _LC7_C22 & !RW
         #  _LC8_C22;

-- Node name is '|POC:15|:812' 
-- Equation name is '_LC8_C22', type is buried 
_LC8_C22 = LCELL( _EQ036);
  _EQ036 =  _LC2_C22 &  _LC4_C19 & !RW;

-- Node name is '|POC:15|:1462' 
-- Equation name is '_LC5_C22', type is buried 
_LC5_C22 = LCELL( _EQ037);
  _EQ037 = !_LC4_C22 & !_LC6_C22;

-- Node name is '|POC:15|:1465' 
-- Equation name is '_LC1_C36', type is buried 
!_LC1_C36 = _LC1_C36~NOT;
_LC1_C36~NOT = LCELL( _LC4_C22);



Project Information                                         d:\ppoc\pocpoc.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10KE' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 49,238K