📄 pocpoc.rpt
字号:
32 - - F -- TRI 0 1 0 0 PD2
18 - - C -- TRI 0 1 0 0 PD3
28 - - E -- TRI 0 1 0 0 PD4
31 - - F -- TRI 0 1 0 0 PD5
14 - - C -- TRI 0 1 0 0 PD6
20 - - D -- TRI 0 1 0 0 PD7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\ppoc\pocpoc.rpt
pocpoc
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 22 DFFE + 0 1 0 2 |POC:15|current_state1 (|POC:15|:43)
- 6 - C 22 DFFE + 1 2 0 1 |POC:15|current_state0 (|POC:15|:44)
- 4 - C 34 DFFE + 2 1 0 1 |POC:15|SR6 (|POC:15|:48)
- 2 - F 29 DFFE + 2 1 0 1 |POC:15|SR5 (|POC:15|:49)
- 4 - E 29 DFFE + 2 1 0 1 |POC:15|SR4 (|POC:15|:50)
- 2 - C 34 DFFE + 2 1 0 1 |POC:15|SR3 (|POC:15|:51)
- 1 - F 29 DFFE + 2 1 0 1 |POC:15|SR2 (|POC:15|:52)
- 2 - E 29 DFFE + 2 1 0 1 |POC:15|SR1 (|POC:15|:53)
- 7 - C 22 DFFE + 2 1 0 1 |POC:15|SR0 (|POC:15|:54)
- 2 - C 19 DFFE + 1 1 1 1 |POC:15|BR7 (|POC:15|:55)
- 3 - C 34 DFFE + 1 1 1 1 |POC:15|BR6 (|POC:15|:56)
- 3 - F 29 DFFE + 1 1 1 1 |POC:15|BR5 (|POC:15|:57)
- 5 - E 29 DFFE + 1 1 1 1 |POC:15|BR4 (|POC:15|:58)
- 6 - C 34 DFFE + 1 1 1 1 |POC:15|BR3 (|POC:15|:59)
- 5 - F 29 DFFE + 1 1 1 1 |POC:15|BR2 (|POC:15|:60)
- 1 - E 29 DFFE + 1 1 1 1 |POC:15|BR1 (|POC:15|:61)
- 2 - C 22 DFFE + 1 1 1 1 |POC:15|BR0 (|POC:15|:62)
- 3 - C 22 OR2 s 1 3 0 8 |POC:15|~387~1
- 3 - C 19 AND2 s 4 0 0 17 |POC:15|~591~1
- 4 - C 19 AND2 s 4 0 0 11 |POC:15|~603~1
- 1 - C 19 OR2 ! 1 2 0 0 |POC:15|:704
- 8 - C 19 OR2 1 3 1 0 |POC:15|:705
- 5 - C 19 AND2 1 2 0 1 |POC:15|:707
- 5 - C 34 OR2 1 3 1 0 |POC:15|:720
- 8 - C 34 AND2 1 2 0 1 |POC:15|:722
- 7 - F 29 OR2 1 3 1 0 |POC:15|:735
- 8 - F 29 AND2 1 2 0 1 |POC:15|:737
- 7 - E 29 OR2 1 3 1 0 |POC:15|:750
- 8 - E 29 AND2 1 2 0 1 |POC:15|:752
- 1 - C 34 OR2 1 3 1 0 |POC:15|:765
- 7 - C 34 AND2 1 2 0 1 |POC:15|:767
- 6 - F 29 OR2 1 3 1 0 |POC:15|:780
- 4 - F 29 AND2 1 2 0 1 |POC:15|:782
- 3 - E 29 OR2 1 3 1 0 |POC:15|:795
- 6 - E 29 AND2 1 2 0 1 |POC:15|:797
- 1 - C 22 OR2 1 3 1 0 |POC:15|:810
- 8 - C 22 AND2 1 2 0 1 |POC:15|:812
- 5 - C 22 AND2 0 2 0 4 |POC:15|:1462
- 1 - C 36 AND2 ! 0 1 0 0 |POC:15|:1465
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\ppoc\pocpoc.rpt
pocpoc
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 8/144( 5%) 0/ 72( 0%) 9/ 72( 12%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 4/144( 2%) 0/ 72( 0%) 5/ 72( 6%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
F: 7/144( 4%) 0/ 72( 0%) 3/ 72( 4%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\ppoc\pocpoc.rpt
pocpoc
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 CLOCK
Device-Specific Information: d:\ppoc\pocpoc.rpt
pocpoc
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 2 RESET
Device-Specific Information: d:\ppoc\pocpoc.rpt
pocpoc
** EQUATIONS **
ADDRESS0 : INPUT;
ADDRESS1 : INPUT;
ADDRESS2 : INPUT;
CLOCK : INPUT;
CS : INPUT;
DATAIN0 : INPUT;
DATAIN1 : INPUT;
DATAIN2 : INPUT;
DATAIN3 : INPUT;
DATAIN4 : INPUT;
DATAIN5 : INPUT;
DATAIN6 : INPUT;
DATAIN7 : INPUT;
RESET : INPUT;
RW : INPUT;
-- Node name is 'DATAOUT0'
-- Equation name is 'DATAOUT0', type is output
DATAOUT0 = TRI(_LC1_C22, !_LC1_C19);
-- Node name is 'DATAOUT1'
-- Equation name is 'DATAOUT1', type is output
DATAOUT1 = TRI(_LC3_E29, !_LC1_C19);
-- Node name is 'DATAOUT2'
-- Equation name is 'DATAOUT2', type is output
DATAOUT2 = TRI(_LC6_F29, !_LC1_C19);
-- Node name is 'DATAOUT3'
-- Equation name is 'DATAOUT3', type is output
DATAOUT3 = TRI(_LC1_C34, !_LC1_C19);
-- Node name is 'DATAOUT4'
-- Equation name is 'DATAOUT4', type is output
DATAOUT4 = TRI(_LC7_E29, !_LC1_C19);
-- Node name is 'DATAOUT5'
-- Equation name is 'DATAOUT5', type is output
DATAOUT5 = TRI(_LC7_F29, !_LC1_C19);
-- Node name is 'DATAOUT6'
-- Equation name is 'DATAOUT6', type is output
DATAOUT6 = TRI(_LC5_C34, !_LC1_C19);
-- Node name is 'DATAOUT7'
-- Equation name is 'DATAOUT7', type is output
DATAOUT7 = TRI(_LC8_C19, !_LC1_C19);
-- Node name is 'PD0'
-- Equation name is 'PD0', type is output
PD0 = TRI(_LC2_C22, !_LC1_C36);
-- Node name is 'PD1'
-- Equation name is 'PD1', type is output
PD1 = TRI(_LC1_E29, !_LC1_C36);
-- Node name is 'PD2'
-- Equation name is 'PD2', type is output
PD2 = TRI(_LC5_F29, !_LC1_C36);
-- Node name is 'PD3'
-- Equation name is 'PD3', type is output
PD3 = TRI(_LC6_C34, !_LC1_C36);
-- Node name is 'PD4'
-- Equation name is 'PD4', type is output
PD4 = TRI(_LC5_E29, !_LC1_C36);
-- Node name is 'PD5'
-- Equation name is 'PD5', type is output
PD5 = TRI(_LC3_F29, !_LC1_C36);
-- Node name is 'PD6'
-- Equation name is 'PD6', type is output
PD6 = TRI(_LC3_C34, !_LC1_C36);
-- Node name is 'PD7'
-- Equation name is 'PD7', type is output
PD7 = TRI(_LC2_C19, !_LC1_C36);
-- Node name is '|POC:15|:62' = '|POC:15|BR0'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = DFFE( _EQ001, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ001 = DATAIN0 & !_LC3_C22
# _LC2_C22 & _LC3_C22;
-- Node name is '|POC:15|:61' = '|POC:15|BR1'
-- Equation name is '_LC1_E29', type is buried
_LC1_E29 = DFFE( _EQ002, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ002 = DATAIN1 & !_LC3_C22
# _LC1_E29 & _LC3_C22;
-- Node name is '|POC:15|:60' = '|POC:15|BR2'
-- Equation name is '_LC5_F29', type is buried
_LC5_F29 = DFFE( _EQ003, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ003 = DATAIN2 & !_LC3_C22
# _LC3_C22 & _LC5_F29;
-- Node name is '|POC:15|:59' = '|POC:15|BR3'
-- Equation name is '_LC6_C34', type is buried
_LC6_C34 = DFFE( _EQ004, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ004 = DATAIN3 & !_LC3_C22
# _LC3_C22 & _LC6_C34;
-- Node name is '|POC:15|:58' = '|POC:15|BR4'
-- Equation name is '_LC5_E29', type is buried
_LC5_E29 = DFFE( _EQ005, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ005 = DATAIN4 & !_LC3_C22
# _LC3_C22 & _LC5_E29;
-- Node name is '|POC:15|:57' = '|POC:15|BR5'
-- Equation name is '_LC3_F29', type is buried
_LC3_F29 = DFFE( _EQ006, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ006 = DATAIN5 & !_LC3_C22
# _LC3_C22 & _LC3_F29;
-- Node name is '|POC:15|:56' = '|POC:15|BR6'
-- Equation name is '_LC3_C34', type is buried
_LC3_C34 = DFFE( _EQ007, GLOBAL( CLOCK), VCC, VCC, VCC);
_EQ007 = DATAIN6 & !_LC3_C22
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