poc.vhd

简单的POC实现与打印机

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity POC is
port(RW,CS,RDY,CLK,RESET: in std_logic;
	 IRQ,TR: out std_logic;
	 A: in std_logic_vector(2 downto 0);
	 Din: in std_logic_vector(7 downto 0);
	 Dout:out std_logic_vector(7 downto 0);
	 PD: out std_logic_vector(7 downto 0);
	 SR_register: out std_logic_vector(7 downto 0)
	 );
end POC;

architecture behave of POC is

signal BR,SR:std_logic_vector(7 downto 0);
type state is (waitdata,waitprint,print);
signal current_state,next_state: state:=waitdata;

begin

	process(CLK,RESET)
	begin
		if(reset='1')then
			current_state<=waitdata;
		elsif(clk'event and clk='1')then
			current_state<=next_state;
		end if;
	end process;

	IRQ<=not(SR(7) and SR(0));


	process(CS,RW,A,current_state,SR,BR,CLK)
		begin 
			if(CLK'event and CLK='1')then
				if(CS='1' and RW='1' and A="000")then
				 
					SR<=Din;
				elsif(CS='1' and RW='1' and A="001" and SR(7)='1')then
					BR<=Din;
				end if;
			end if;

			if(CS='1' and RW='0' and A="000")then
				Dout<=SR;
			elsif(CS='1' and RW='0' and A="001")then
				Dout<=BR;
			else
				Dout<="ZZZZZZZZ";
			end if;

			case current_state is
				 	when waitdata=>
						if(CS='1' and RW='1' and A="000")then
							 SR(7)<=Din(7);
					    else SR(7)<='1';
						end if;
					 when others=>
						if(CS='1' and RW='1' and A="000")then
							 SR(7)<=Din(7);
					    else SR(7)<='0';
						end if;
				 end case;


			SR_register<=SR;
	end process;


	process(current_state,RDY, CS, RW, A, BR)
		begin
			case current_state is
				when waitdata=>
					-- SR(7)<='1';
					 PD<="ZZZZZZZZ";
					 TR<='0';
					 if(CS='1'and rw='1'and A="001")then
						 next_state<=waitprint;
					 else 
						 next_state<=waitdata;
					 end if;
				when waitprint=>
					-- SR(7)<='0';
					 TR<='1';
					 PD<="ZZZZZZZZ";
					 if(RDY='1')then
						 next_state<=print;
					 else 	
						 next_state<=waitprint;
					 end if;
				when print=>
					-- SR(7)<='0';
					 PD<=BR;
					 TR<='0';
					 IF(RDY='0')then
						next_state<=waitdata;
					 else
						next_state<=print;
					 end if;

			 end case;
	 end process;
end behave;