📄 printer.rpt
字号:
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\ppoc\printer.rpt
printer
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 26 OR2 1 1 0 2 :21
- 1 - C 28 AND2 ! 1 1 0 4 :23
- 4 - C 26 OR2 1 3 1 1 :24
- 6 - C 26 OR2 ! 1 2 0 1 |74193:2|:6
- 1 - C 26 OR2 ! 0 4 0 1 |74193:2|:22
- 1 - C 34 DFFE 0 1 0 1 |74193:2|QD (|74193:2|:23)
- 1 - C 27 DFFE ! 0 1 0 2 |74193:2|QC (|74193:2|:24)
- 7 - C 26 DFFE 0 1 0 3 |74193:2|QB (|74193:2|:25)
- 5 - C 26 DFFE ! 0 1 0 4 |74193:2|QA (|74193:2|:26)
- 8 - C 26 AND2 s 1 3 0 1 |74193:2|BON~1 (|74193:2|~28~1)
- 2 - C 26 OR2 ! 1 3 0 1 |74193:2|:50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\ppoc\printer.rpt
printer
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/144( 0%) 0/ 72( 0%) 5/ 72( 6%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\ppoc\printer.rpt
printer
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 2 :21
LCELL 1 |74193:2|:6
LCELL 1 |74193:2|:22
LCELL 1 |74193:2|:50
Device-Specific Information: d:\ppoc\printer.rpt
printer
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 TR
Device-Specific Information: d:\ppoc\printer.rpt
printer
** EQUATIONS **
CLOCK : INPUT;
RESET : INPUT;
TR : INPUT;
-- Node name is 'RDY'
-- Equation name is 'RDY', type is output
RDY = _LC4_C26;
-- Node name is '|74193:2|~28~1' = '|74193:2|BON~1'
-- Equation name is '_LC8_C26', type is buried
-- synthesized logic cell
_LC8_C26 = LCELL( _EQ001);
_EQ001 = CLOCK & !_LC1_C27 & !_LC5_C26 & !_LC7_C26;
-- Node name is '|74193:2|:26' = '|74193:2|QA'
-- Equation name is '_LC5_C26', type is buried
!_LC5_C26 = _LC5_C26~NOT;
_LC5_C26~NOT = DFFE( _LC5_C26, _LC3_C26, GLOBAL(!TR), VCC, VCC);
-- Node name is '|74193:2|:25' = '|74193:2|QB'
-- Equation name is '_LC7_C26', type is buried
_LC7_C26 = DFFE(!_LC7_C26, !_LC6_C26, GLOBAL(!TR), VCC, VCC);
-- Node name is '|74193:2|:24' = '|74193:2|QC'
-- Equation name is '_LC1_C27', type is buried
!_LC1_C27 = _LC1_C27~NOT;
_LC1_C27~NOT = DFFE( _LC1_C27, !_LC2_C26, GLOBAL(!TR), VCC, VCC);
-- Node name is '|74193:2|:23' = '|74193:2|QD'
-- Equation name is '_LC1_C34', type is buried
_LC1_C34 = DFFE(!_LC1_C34, !_LC1_C26, GLOBAL(!TR), VCC, VCC);
-- Node name is '|74193:2|:6'
-- Equation name is '_LC6_C26', type is buried
!_LC6_C26 = _LC6_C26~NOT;
_LC6_C26~NOT = LCELL( _EQ002);
_EQ002 = !_LC1_C28
# !CLOCK
# _LC5_C26;
-- Node name is '|74193:2|:22'
-- Equation name is '_LC1_C26', type is buried
!_LC1_C26 = _LC1_C26~NOT;
_LC1_C26~NOT = LCELL( _EQ003);
_EQ003 = _LC5_C26
# _LC3_C26
# _LC7_C26
# _LC1_C27;
-- Node name is '|74193:2|:50'
-- Equation name is '_LC2_C26', type is buried
!_LC2_C26 = _LC2_C26~NOT;
_LC2_C26~NOT = LCELL( _EQ004);
_EQ004 = !_LC1_C28
# !CLOCK
# _LC5_C26
# _LC7_C26;
-- Node name is ':21'
-- Equation name is '_LC3_C26', type is buried
_LC3_C26 = LCELL( _EQ005);
_EQ005 = !_LC1_C28
# !CLOCK;
-- Node name is ':23'
-- Equation name is '_LC1_C28', type is buried
!_LC1_C28 = _LC1_C28~NOT;
_LC1_C28~NOT = LCELL( _EQ006);
_EQ006 = _LC4_C26 & !TR;
-- Node name is ':24'
-- Equation name is '_LC4_C26', type is buried
_LC4_C26 = LCELL( _EQ007);
_EQ007 = !_LC1_C34 & _LC8_C26
# !_LC1_C28
# !RESET;
Project Information d:\ppoc\printer.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10KE' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 46,187K
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