📄 poc.rpt
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_EQ008 = A0 & !A1 & !A2 & BR5 & CS & !RW
# !A0 & !A1 & !A2 & CS & !RW & SR_register5;
-- Node name is 'Dout6'
-- Equation name is 'Dout6', location is LC025, type is output.
Dout6 = TRI(_LC025, GLOBAL(!~PIN001));
_LC025 = LCELL( _EQ009 $ GND);
_EQ009 = A0 & !A1 & !A2 & BR6 & CS & !RW
# !A0 & !A1 & !A2 & CS & !RW & SR_register6;
-- Node name is 'Dout7'
-- Equation name is 'Dout7', location is LC053, type is output.
Dout7 = TRI(_LC053, GLOBAL(!~PIN001));
_LC053 = LCELL( _EQ010 $ GND);
_EQ010 = !A0 & !A1 & !A2 & CS & !current_state0 & !current_state1 & !RW
# A0 & !A1 & !A2 & BR7 & CS & !RW;
-- Node name is 'IRQ'
-- Equation name is 'IRQ', location is LC064, type is output.
IRQ = LCELL( _EQ011 $ VCC);
_EQ011 = !A0 & !A1 & !A2 & CS & Din7 & RW & SR_register0
# !current_state0 & !current_state1 & SR_register0 & _X001;
_X001 = EXP(!A0 & !A1 & !A2 & CS & RW);
-- Node name is 'PD0' = 'BR0'
-- Equation name is 'PD0', location is LC052, type is output.
PD0 = TRI(BR0, GLOBAL(!~PIN003));
BR0 = TFFE( _EQ012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = A0 & !A1 & !A2 & !BR0 & CS & !current_state0 & !current_state1 &
Din0 & RW
# A0 & !A1 & !A2 & BR0 & CS & !current_state0 & !current_state1 &
!Din0 & RW;
-- Node name is 'PD1' = 'BR1'
-- Equation name is 'PD1', location is LC051, type is output.
PD1 = TRI(BR1, GLOBAL(!~PIN003));
BR1 = TFFE( _EQ013, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = A0 & !A1 & !A2 & !BR1 & CS & !current_state0 & !current_state1 &
Din1 & RW
# A0 & !A1 & !A2 & BR1 & CS & !current_state0 & !current_state1 &
!Din1 & RW;
-- Node name is 'PD2' = 'BR2'
-- Equation name is 'PD2', location is LC043, type is output.
PD2 = TRI(BR2, GLOBAL(!~PIN003));
BR2 = TFFE( _EQ014, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = A0 & !A1 & !A2 & !BR2 & CS & !current_state0 & !current_state1 &
Din2 & RW
# A0 & !A1 & !A2 & BR2 & CS & !current_state0 & !current_state1 &
!Din2 & RW;
-- Node name is 'PD3' = 'BR3'
-- Equation name is 'PD3', location is LC037, type is output.
PD3 = TRI(BR3, GLOBAL(!~PIN003));
BR3 = TFFE( _EQ015, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = A0 & !A1 & !A2 & !BR3 & CS & !current_state0 & !current_state1 &
Din3 & RW
# A0 & !A1 & !A2 & BR3 & CS & !current_state0 & !current_state1 &
!Din3 & RW;
-- Node name is 'PD4' = 'BR4'
-- Equation name is 'PD4', location is LC035, type is output.
PD4 = TRI(BR4, GLOBAL(!~PIN003));
BR4 = TFFE( _EQ016, GLOBAL( CLK), VCC, VCC, VCC);
_EQ016 = A0 & !A1 & !A2 & !BR4 & CS & !current_state0 & !current_state1 &
Din4 & RW
# A0 & !A1 & !A2 & BR4 & CS & !current_state0 & !current_state1 &
!Din4 & RW;
-- Node name is 'PD5' = 'BR5'
-- Equation name is 'PD5', location is LC033, type is output.
PD5 = TRI(BR5, GLOBAL(!~PIN003));
BR5 = TFFE( _EQ017, GLOBAL( CLK), VCC, VCC, VCC);
_EQ017 = A0 & !A1 & !A2 & !BR5 & CS & !current_state0 & !current_state1 &
Din5 & RW
# A0 & !A1 & !A2 & BR5 & CS & !current_state0 & !current_state1 &
!Din5 & RW;
-- Node name is 'PD6' = 'BR6'
-- Equation name is 'PD6', location is LC017, type is output.
PD6 = TRI(BR6, GLOBAL(!~PIN003));
BR6 = TFFE( _EQ018, GLOBAL( CLK), VCC, VCC, VCC);
_EQ018 = A0 & !A1 & !A2 & !BR6 & CS & !current_state0 & !current_state1 &
Din6 & RW
# A0 & !A1 & !A2 & BR6 & CS & !current_state0 & !current_state1 &
!Din6 & RW;
-- Node name is 'PD7' = 'BR7'
-- Equation name is 'PD7', location is LC049, type is output.
PD7 = TRI(BR7, GLOBAL(!~PIN003));
BR7 = TFFE( _EQ019, GLOBAL( CLK), VCC, VCC, VCC);
_EQ019 = A0 & !A1 & !A2 & !BR7 & CS & !current_state0 & !current_state1 &
Din7 & RW
# A0 & !A1 & !A2 & BR7 & CS & !current_state0 & !current_state1 &
!Din7 & RW;
-- Node name is 'SR_register0' = 'SR0'
-- Equation name is 'SR_register0', location is LC056, type is output.
SR_register0 = TFFE( _EQ020, GLOBAL( CLK), VCC, VCC, VCC);
_EQ020 = !A0 & !A1 & !A2 & CS & Din0 & RW & !SR_register0
# !A0 & !A1 & !A2 & CS & !Din0 & RW & SR_register0;
-- Node name is 'SR_register1' = 'SR1'
-- Equation name is 'SR_register1', location is LC057, type is output.
SR_register1 = TFFE( _EQ021, GLOBAL( CLK), VCC, VCC, VCC);
_EQ021 = !A0 & !A1 & !A2 & CS & Din1 & RW & !SR_register1
# !A0 & !A1 & !A2 & CS & !Din1 & RW & SR_register1;
-- Node name is 'SR_register2' = 'SR2'
-- Equation name is 'SR_register2', location is LC048, type is output.
SR_register2 = TFFE( _EQ022, GLOBAL( CLK), VCC, VCC, VCC);
_EQ022 = !A0 & !A1 & !A2 & CS & Din2 & RW & !SR_register2
# !A0 & !A1 & !A2 & CS & !Din2 & RW & SR_register2;
-- Node name is 'SR_register3' = 'SR3'
-- Equation name is 'SR_register3', location is LC036, type is output.
SR_register3 = TFFE( _EQ023, GLOBAL( CLK), VCC, VCC, VCC);
_EQ023 = !A0 & !A1 & !A2 & CS & Din3 & RW & !SR_register3
# !A0 & !A1 & !A2 & CS & !Din3 & RW & SR_register3;
-- Node name is 'SR_register4' = 'SR4'
-- Equation name is 'SR_register4', location is LC038, type is output.
SR_register4 = TFFE( _EQ024, GLOBAL( CLK), VCC, VCC, VCC);
_EQ024 = !A0 & !A1 & !A2 & CS & Din4 & RW & !SR_register4
# !A0 & !A1 & !A2 & CS & !Din4 & RW & SR_register4;
-- Node name is 'SR_register5' = 'SR5'
-- Equation name is 'SR_register5', location is LC040, type is output.
SR_register5 = TFFE( _EQ025, GLOBAL( CLK), VCC, VCC, VCC);
_EQ025 = !A0 & !A1 & !A2 & CS & Din5 & RW & !SR_register5
# !A0 & !A1 & !A2 & CS & !Din5 & RW & SR_register5;
-- Node name is 'SR_register6' = 'SR6'
-- Equation name is 'SR_register6', location is LC022, type is output.
SR_register6 = TFFE( _EQ026, GLOBAL( CLK), VCC, VCC, VCC);
_EQ026 = !A0 & !A1 & !A2 & CS & Din6 & RW & !SR_register6
# !A0 & !A1 & !A2 & CS & !Din6 & RW & SR_register6;
-- Node name is 'SR_register7'
-- Equation name is 'SR_register7', location is LC061, type is output.
SR_register7 = LCELL( _EQ027 $ GND);
_EQ027 = !A0 & !A1 & !A2 & CS & Din7 & RW
# !current_state0 & !current_state1 & _X001;
_X001 = EXP(!A0 & !A1 & !A2 & CS & RW);
-- Node name is 'TR'
-- Equation name is 'TR', location is LC062, type is output.
TR = LCELL( _EQ028 $ current_state0);
_EQ028 = current_state0 & current_state1;
-- Node name is '~702~1'
-- Equation name is '~702~1', location is LC024, type is output.
~PIN002 = LCELL( _EQ029 $ VCC);
_EQ029 = !A1 & !A2 & CS & !RW;
-- Node name is '~1465~1'
-- Equation name is '~1465~1', location is LC054, type is output.
~PIN004 = LCELL( current_state1 $ VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\ppoc\poc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,596K
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