📄 poc.rpt
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59 57 D FF + t 0 0 0 6 1 2 0 SR_register1 (:53)
50 48 C FF + t 0 0 0 6 1 2 0 SR_register2 (:52)
39 36 C FF + t 0 0 0 6 1 2 0 SR_register3 (:51)
41 38 C FF + t 0 0 0 6 1 2 0 SR_register4 (:50)
42 40 C FF + t 0 0 0 6 1 2 0 SR_register5 (:49)
28 22 B FF + t 0 0 0 6 1 2 0 SR_register6 (:48)
62 61 D OUTPUT t 1 1 0 6 2 0 0 SR_register7
64 62 D OUTPUT t 0 0 0 0 2 0 0 TR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\ppoc\poc.rpt
poc
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 55 D DFFE + t 0 0 0 2 2 13 2 current_state1 (:43)
- 50 D DFFE + t 0 0 0 7 2 12 2 current_state0 (:44)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\ppoc\poc.rpt
poc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------- LC25 Dout6
| +----- LC17 PD6
| | +--- LC24 ~PIN002
| | | +- LC22 SR_register6
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'B'
LC | | | | | A B C D | Logic cells that feed LAB 'B':
LC17 -> * * - - | - * - - | <-- PD6
LC22 -> * - - * | - * - - | <-- SR_register6
Pin
17 -> * * - * | - * * * | <-- A0
15 -> * * * * | - * * * | <-- A1
14 -> * * * * | - * * * | <-- A2
67 -> - - - - | - - - - | <-- CLK
13 -> * * * * | - * * * | <-- CS
7 -> - * - * | - * - - | <-- Din6
68 -> - - - - | - - - - | <-- ~PIN001
2 -> - - - - | - - - - | <-- ~PIN003
18 -> * * * * | - * * * | <-- RW
LC55 -> - * - - | - * * * | <-- current_state1
LC50 -> - * - - | - * * * | <-- current_state0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\ppoc\poc.rpt
poc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------- LC46 Dout2
| +--------------------- LC45 Dout3
| | +------------------- LC44 Dout4
| | | +----------------- LC41 Dout5
| | | | +--------------- LC43 PD2
| | | | | +------------- LC37 PD3
| | | | | | +----------- LC35 PD4
| | | | | | | +--------- LC33 PD5
| | | | | | | | +------- LC48 SR_register2
| | | | | | | | | +----- LC36 SR_register3
| | | | | | | | | | +--- LC38 SR_register4
| | | | | | | | | | | +- LC40 SR_register5
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC43 -> * - - - * - - - - - - - | - - * - | <-- PD2
LC37 -> - * - - - * - - - - - - | - - * - | <-- PD3
LC35 -> - - * - - - * - - - - - | - - * - | <-- PD4
LC33 -> - - - * - - - * - - - - | - - * - | <-- PD5
LC48 -> * - - - - - - - * - - - | - - * - | <-- SR_register2
LC36 -> - * - - - - - - - * - - | - - * - | <-- SR_register3
LC38 -> - - * - - - - - - - * - | - - * - | <-- SR_register4
LC40 -> - - - * - - - - - - - * | - - * - | <-- SR_register5
Pin
17 -> * * * * * * * * * * * * | - * * * | <-- A0
15 -> * * * * * * * * * * * * | - * * * | <-- A1
14 -> * * * * * * * * * * * * | - * * * | <-- A2
67 -> - - - - - - - - - - - - | - - - - | <-- CLK
13 -> * * * * * * * * * * * * | - * * * | <-- CS
32 -> - - - - * - - - * - - - | - - * - | <-- Din2
30 -> - - - - - * - - - * - - | - - * - | <-- Din3
29 -> - - - - - - * - - - * - | - - * - | <-- Din4
4 -> - - - - - - - * - - - * | - - * - | <-- Din5
68 -> - - - - - - - - - - - - | - - - - | <-- ~PIN001
2 -> - - - - - - - - - - - - | - - - - | <-- ~PIN003
18 -> * * * * * * * * * * * * | - * * * | <-- RW
LC55 -> - - - - * * * * - - - - | - * * * | <-- current_state1
LC50 -> - - - - * * * * - - - - | - * * * | <-- current_state0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\ppoc\poc.rpt
poc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--------------------------- LC60 Dout0
| +------------------------- LC59 Dout1
| | +----------------------- LC53 Dout7
| | | +--------------------- LC64 IRQ
| | | | +------------------- LC52 PD0
| | | | | +----------------- LC51 PD1
| | | | | | +--------------- LC49 PD7
| | | | | | | +------------- LC54 ~PIN004
| | | | | | | | +----------- LC56 SR_register0
| | | | | | | | | +--------- LC57 SR_register1
| | | | | | | | | | +------- LC61 SR_register7
| | | | | | | | | | | +----- LC62 TR
| | | | | | | | | | | | +--- LC55 current_state1
| | | | | | | | | | | | | +- LC50 current_state0
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC52 -> * - - - * - - - - - - - - - | - - - * | <-- PD0
LC51 -> - * - - - * - - - - - - - - | - - - * | <-- PD1
LC49 -> - - * - - - * - - - - - - - | - - - * | <-- PD7
LC56 -> * - - * - - - - * - - - - - | - - - * | <-- SR_register0
LC57 -> - * - - - - - - - * - - - - | - - - * | <-- SR_register1
LC55 -> - - * * * * * * - - * * * * | - * * * | <-- current_state1
LC50 -> - - * * * * * - - - * * * * | - * * * | <-- current_state0
Pin
17 -> * * * * * * * - * * * - - * | - * * * | <-- A0
15 -> * * * * * * * - * * * - - * | - * * * | <-- A1
14 -> * * * * * * * - * * * - - * | - * * * | <-- A2
67 -> - - - - - - - - - - - - - - | - - - - | <-- CLK
13 -> * * * * * * * - * * * - - * | - * * * | <-- CS
12 -> - - - - * - - - * - - - - - | - - - * | <-- Din0
5 -> - - - - - * - - - * - - - - | - - - * | <-- Din1
8 -> - - - * - - * - - - * - - - | - - - * | <-- Din7
68 -> - - - - - - - - - - - - - - | - - - - | <-- ~PIN001
2 -> - - - - - - - - - - - - - - | - - - - | <-- ~PIN003
10 -> - - - - - - - - - - - - * * | - - - * | <-- RDY
9 -> - - - - - - - - - - - - * * | - - - * | <-- RESET
18 -> * * * * * * * - * * * - - * | - * * * | <-- RW
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\ppoc\poc.rpt
poc
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
CLK : INPUT;
CS : INPUT;
Din0 : INPUT;
Din1 : INPUT;
Din2 : INPUT;
Din3 : INPUT;
Din4 : INPUT;
Din5 : INPUT;
Din6 : INPUT;
Din7 : INPUT;
RDY : INPUT;
RESET : INPUT;
RW : INPUT;
~PIN001 : INPUT;
~PIN003 : INPUT;
-- Node name is ':44' = 'current_state0'
-- Equation name is 'current_state0', location is LC050, type is buried.
current_state0 = DFFE( _EQ001 $ GND, GLOBAL( CLK), !RESET, VCC, VCC);
_EQ001 = A0 & !A1 & !A2 & CS & !current_state0 & !current_state1 & RW
# current_state0 & !current_state1 & RDY;
-- Node name is ':43' = 'current_state1'
-- Equation name is 'current_state1', location is LC055, type is buried.
current_state1 = DFFE( _EQ002 $ !RDY, GLOBAL( CLK), !RESET, VCC, VCC);
_EQ002 = !current_state0 & !current_state1 & !RDY;
-- Node name is 'Dout0'
-- Equation name is 'Dout0', location is LC060, type is output.
Dout0 = TRI(_LC060, GLOBAL(!~PIN001));
_LC060 = LCELL( _EQ003 $ GND);
_EQ003 = A0 & !A1 & !A2 & BR0 & CS & !RW
# !A0 & !A1 & !A2 & CS & !RW & SR_register0;
-- Node name is 'Dout1'
-- Equation name is 'Dout1', location is LC059, type is output.
Dout1 = TRI(_LC059, GLOBAL(!~PIN001));
_LC059 = LCELL( _EQ004 $ GND);
_EQ004 = A0 & !A1 & !A2 & BR1 & CS & !RW
# !A0 & !A1 & !A2 & CS & !RW & SR_register1;
-- Node name is 'Dout2'
-- Equation name is 'Dout2', location is LC046, type is output.
Dout2 = TRI(_LC046, GLOBAL(!~PIN001));
_LC046 = LCELL( _EQ005 $ GND);
_EQ005 = A0 & !A1 & !A2 & BR2 & CS & !RW
# !A0 & !A1 & !A2 & CS & !RW & SR_register2;
-- Node name is 'Dout3'
-- Equation name is 'Dout3', location is LC045, type is output.
Dout3 = TRI(_LC045, GLOBAL(!~PIN001));
_LC045 = LCELL( _EQ006 $ GND);
_EQ006 = A0 & !A1 & !A2 & BR3 & CS & !RW
# !A0 & !A1 & !A2 & CS & !RW & SR_register3;
-- Node name is 'Dout4'
-- Equation name is 'Dout4', location is LC044, type is output.
Dout4 = TRI(_LC044, GLOBAL(!~PIN001));
_LC044 = LCELL( _EQ007 $ GND);
_EQ007 = A0 & !A1 & !A2 & BR4 & CS & !RW
# !A0 & !A1 & !A2 & CS & !RW & SR_register4;
-- Node name is 'Dout5'
-- Equation name is 'Dout5', location is LC041, type is output.
Dout5 = TRI(_LC041, GLOBAL(!~PIN001));
_LC041 = LCELL( _EQ008 $ GND);
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