📄 poc.rpt
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Project Information d:\ppoc\poc.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/09/2008 22:27:47
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
POC
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
poc EPM7064LC68-7 18 28 0 30 1 46 %
User Pins: 16 26 0
Project Information d:\ppoc\poc.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Line 37: File d:\ppoc\poc.vhd: Found multiple assignments to the same signal or signal bit "SR7" in a Process Statement -- only the last assignment will take effect
Project Information d:\ppoc\poc.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK' chosen for auto global Clock
Project Information d:\ppoc\poc.rpt
** MULTIPLE PIN CONNECTIONS **
For node name '~702~2' (Same as node '~PIN001')
For node name '~702~1' (Same as node '~PIN002')
Connect: {poc@68, poc@27}
For node name '~1465~2' (Same as node '~PIN003')
For node name '~1465~1' (Same as node '~PIN004')
Connect: {poc@2, poc@56}
Device-Specific Information: d:\ppoc\poc.rpt
poc
***** Logic for device 'poc' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: d:\ppoc\poc.rpt
poc
** ERROR SUMMARY **
Info: Chip 'poc' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
S
R
_
r
e
~ ~ g
V P P i
R C I I V s D
E D D D D C N N C t o
S i i G i i I 0 G 0 C G I C e u
E n n N n n N 0 N 0 L N R T I r t
T 7 6 D 1 5 T 3 D 1 K D Q R O 7 0
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
RDY | 10 60 | Dout1
VCCIO | 11 59 | SR_register1
Din0 | 12 58 | GND
CS | 13 57 | SR_register0
A2 | 14 56 | ~PIN004
A1 | 15 55 | Dout7
GND | 16 54 | PD0
A0 | 17 53 | VCCIO
RW | 18 EPM7064LC68-7 52 | PD1
RESERVED | 19 51 | PD7
RESERVED | 20 50 | SR_register2
VCCIO | 21 49 | Dout2
RESERVED | 22 48 | GND
RESERVED | 23 47 | Dout3
RESERVED | 24 46 | Dout4
Dout6 | 25 45 | PD2
GND | 26 44 | Dout5
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
~ S D D V D P G V P P G S P S S V
P R i i C i D N C D D N R D R R C
I _ n n C n 6 D C 5 4 D _ 3 _ _ C
N r 4 3 I 2 I r r r I
0 e O N e e e O
0 g T g g g
2 i i i i
s s s s
t t t t
e e e e
r r r r
6 3 4 5
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\ppoc\poc.rpt
poc
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 4/16( 25%) 7/12( 58%) 0/16( 0%) 10/36( 27%)
C: LC33 - LC48 12/16( 75%) 12/12(100%) 0/16( 0%) 19/36( 52%)
D: LC49 - LC64 14/16( 87%) 12/12(100%) 1/16( 6%) 17/36( 47%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 43/48 ( 89%)
Total logic cells used: 30/64 ( 46%)
Total shareable expanders used: 1/64 ( 1%)
Total Turbo logic cells used: 30/64 ( 46%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 8.26
Total fan-in: 248
Total input pins required: 18
Total output pins required: 28
Total bidirectional pins required: 0
Total logic cells required: 30
Total flipflops required: 17
Total product terms required: 61
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 1
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\ppoc\poc.rpt
poc
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
17 (3) (A) INPUT 0 0 0 0 0 25 1 A0
15 (4) (A) INPUT 0 0 0 0 0 26 1 A1
14 (5) (A) INPUT 0 0 0 0 0 26 1 A2
67 - - INPUT G 0 0 0 0 0 0 0 CLK
13 (6) (A) INPUT 0 0 0 0 0 26 1 CS
12 (8) (A) INPUT 0 0 0 0 0 2 0 Din0
5 (14) (A) INPUT 0 0 0 0 0 2 0 Din1
32 (19) (B) INPUT 0 0 0 0 0 2 0 Din2
30 (20) (B) INPUT 0 0 0 0 0 2 0 Din3
29 (21) (B) INPUT 0 0 0 0 0 2 0 Din4
4 (16) (A) INPUT 0 0 0 0 0 2 0 Din5
7 (13) (A) INPUT 0 0 0 0 0 2 0 Din6
8 (12) (A) INPUT 0 0 0 0 0 3 0 Din7
68 - - INPUT G s 0 0 0 0 0 0 0 ~PIN001
2 - - INPUT G s 0 0 0 0 0 0 0 ~PIN003
10 (9) (A) INPUT 0 0 0 0 0 0 2 RDY
9 (11) (A) INPUT 0 0 0 0 0 0 2 RESET
18 (1) (A) INPUT 0 0 0 0 0 26 1 RW
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\ppoc\poc.rpt
poc
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
61 60 D TRI t 0 0 0 5 2 0 0 Dout0
60 59 D TRI t 0 0 0 5 2 0 0 Dout1
49 46 C TRI t 0 0 0 5 2 0 0 Dout2
47 45 C TRI t 0 0 0 5 2 0 0 Dout3
46 44 C TRI t 0 0 0 5 2 0 0 Dout4
44 41 C TRI t 0 0 0 5 2 0 0 Dout5
25 25 B TRI t 0 0 0 5 2 0 0 Dout6
55 53 D TRI t 0 0 0 5 3 0 0 Dout7
65 64 D OUTPUT t 1 1 0 6 3 0 0 IRQ
54 52 D TRI/FF + t 0 0 0 6 3 2 0 PD0 (:62)
52 51 D TRI/FF + t 0 0 0 6 3 2 0 PD1 (:61)
45 43 C TRI/FF + t 0 0 0 6 3 2 0 PD2 (:60)
40 37 C TRI/FF + t 0 0 0 6 3 2 0 PD3 (:59)
37 35 C TRI/FF + t 0 0 0 6 3 2 0 PD4 (:58)
36 33 C TRI/FF + t 0 0 0 6 3 2 0 PD5 (:57)
33 17 B TRI/FF + t 0 0 0 6 3 2 0 PD6 (:56)
51 49 D TRI/FF + t 0 0 0 6 3 2 0 PD7 (:55)
27 24 B OUTPUT t 0 0 0 4 0 0 0 ~PIN002
56 54 D OUTPUT t 0 0 0 0 1 0 0 ~PIN004
57 56 D FF + t 0 0 0 6 1 3 0 SR_register0 (:54)
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