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VHDL书写VGA源码

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/project/vga/vgasig.vhd" in Library work.
Entity <vgasig> compiled.
Entity <vgasig> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <vgasig> (Architecture <Behavioral>).
INFO:Xst:1739 - HDL ADVISOR - "D:/project/vga/vgasig.vhd" line 8: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <vgasig> analyzed. Unit <vgasig> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vgasig>.
    Related source file is "D:/project/vga/vgasig.vhd".
    Found 1-bit register for signal <hsyncb>.
    Found 1-bit register for signal <vsyncb>.
    Found 1-bit register for signal <enable>.
    Found 10-bit adder for signal <$n0010> created at line 42.
    Found 10-bit adder for signal <$n0011> created at line 57.
    Found 11-bit comparator less for signal <$n0013> created at line 41.
    Found 11-bit comparator less for signal <$n0014> created at line 56.
    Found 11-bit comparator greatequal for signal <$n0016> created at line 96.
    Found 11-bit comparator greatequal for signal <$n0017> created at line 96.
    Found 11-bit comparator greatequal for signal <$n0018> created at line 70.
    Found 11-bit comparator less for signal <$n0019> created at line 70.
    Found 11-bit comparator greatequal for signal <$n0020> created at line 84.
    Found 11-bit comparator less for signal <$n0021> created at line 84.
    Found 10-bit register for signal <hcnt>.
    Found 10-bit register for signal <vcnt>.
    Summary:
	inferred  23 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   8 Comparator(s).
Unit <vgasig> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 10-bit adder                      : 2
# Registers                        : 5
 1-bit register                    : 3
 10-bit register                   : 2
# Comparators                      : 8
 11-bit comparator greatequal      : 4
 11-bit comparator less            : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <vgasig> ...
Loading device for application Rf_Device from file '3s200.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vgasig, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      31  out of   1920     1%  
 Number of Slice Flip Flops:            23  out of   3840     0%  
 Number of 4 input LUTs:                51  out of   3840     1%  
 Number of bonded IOBs:                 25  out of    173    14%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 12    |
hsyncb:Q                           | NONE                   | 11    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.145ns (Maximum Frequency: 162.734MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.482ns
   Maximum combinational path delay: No path found

=========================================================================