vgasig.syr

VHDL书写VGA源码

#      10-bit register             : 2
# Adders/Subtractors               : 2
#      10-bit adder                : 2
# Comparators                      : 8
#      11-bit comparator greatequal: 4
#      11-bit comparator less      : 4

Cell Usage :
# BELS                             : 92
#      GND                         : 1
#      INV                         : 3
#      LUT1_L                      : 18
#      LUT2                        : 1
#      LUT2_L                      : 21
#      LUT3_L                      : 1
#      LUT4                        : 6
#      LUT4_L                      : 4
#      MUXCY                       : 18
#      VCC                         : 1
#      XORCY                       : 18
# FlipFlops/Latches                : 23
#      FDC                         : 20
#      FDP                         : 2
#      FDR                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 24
#      IBUF                        : 1
#      OBUF                        : 23
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      31  out of   1920     1%  
 Number of Slice Flip Flops:            23  out of   3840     0%  
 Number of 4 input LUTs:                51  out of   3840     1%  
 Number of bonded IOBs:                 25  out of    173    14%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 12    |
hsyncb:Q                           | NONE                   | 11    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.145ns (Maximum Frequency: 162.734MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.482ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clock'
  Clock period: 6.089ns (frequency: 164.231MHz)
  Total number of paths / destination ports: 114 / 12
-------------------------------------------------------------------------
Delay:               6.089ns (Levels of Logic = 11)
  Source:            hcnt_1 (FF)
  Destination:       hcnt_9 (FF)
  Source Clock:      clock rising
  Destination Clock: clock rising

  Data Path: hcnt_1 to hcnt_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.720   1.216  hcnt_1 (hcnt_1)
     LUT1_L:I0->LO         1   0.551   0.000  hcnt_1_rt (hcnt_1_rt)
     MUXCY:S->O            1   0.500   0.000  vgasig__n0010<1>cy (vgasig__n0010<1>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0010<2>cy (vgasig__n0010<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0010<3>cy (vgasig__n0010<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0010<4>cy (vgasig__n0010<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0010<5>cy (vgasig__n0010<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0010<6>cy (vgasig__n0010<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0010<7>cy (vgasig__n0010<7>_cyo)
     MUXCY:CI->O           0   0.064   0.000  vgasig__n0010<8>cy (vgasig__n0010<8>_cyo)
     XORCY:CI->O           1   0.904   0.996  vgasig__n0010<9>_xor (_n0010<9>)
     LUT2_L:I1->LO         1   0.551   0.000  _n0007<9>1 (_n0007<9>)
     FDC:D                     0.203          hcnt_9
    ----------------------------------------
    Total                      6.089ns (3.877ns logic, 2.212ns route)
                                       (63.7% logic, 36.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'hsyncb:Q'
  Clock period: 6.145ns (frequency: 162.734MHz)
  Total number of paths / destination ports: 165 / 11
-------------------------------------------------------------------------
Delay:               6.145ns (Levels of Logic = 9)
  Source:            vcnt_1 (FF)
  Destination:       vcnt_7 (FF)
  Source Clock:      hsyncb:Q rising
  Destination Clock: hsyncb:Q rising

  Data Path: vcnt_1 to vcnt_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   0.720   1.256  vcnt_1 (vcnt_1)
     LUT1_L:I0->LO         1   0.551   0.000  vcnt_1_rt (vcnt_1_rt)
     MUXCY:S->O            1   0.500   0.000  vgasig__n0011<1>cy (vgasig__n0011<1>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0011<2>cy (vgasig__n0011<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0011<3>cy (vgasig__n0011<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0011<4>cy (vgasig__n0011<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0011<5>cy (vgasig__n0011<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  vgasig__n0011<6>cy (vgasig__n0011<6>_cyo)
     XORCY:CI->O           1   0.904   1.140  vgasig__n0011<7>_xor (_n0011<7>)
     LUT2_L:I0->LO         1   0.551   0.000  _n0008<7>1 (_n0008<7>)
     FDC:D                     0.203          vcnt_7
    ----------------------------------------
    Total                      6.145ns (3.749ns logic, 2.396ns route)
                                       (61.0% logic, 39.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'hsyncb:Q'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              7.285ns (Levels of Logic = 1)
  Source:            vcnt_9 (FF)
  Destination:       Yaddr<9> (PAD)
  Source Clock:      hsyncb:Q rising

  Data Path: vcnt_9 to Yaddr<9>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.720   0.921  vcnt_9 (vcnt_9)
     OBUF:I->O                 5.644          Yaddr_9_OBUF (Yaddr<9>)
    ----------------------------------------
    Total                      7.285ns (6.364ns logic, 0.921ns route)
                                       (87.4% logic, 12.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              7.482ns (Levels of Logic = 1)
  Source:            hsyncb (FF)
  Destination:       hsyncb (PAD)
  Source Clock:      clock rising

  Data Path: hsyncb to hsyncb
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q             12   0.720   1.118  hsyncb (hsyncb_OBUF)
     OBUF:I->O                 5.644          hsyncb_OBUF (hsyncb)
    ----------------------------------------
    Total                      7.482ns (6.364ns logic, 1.118ns route)
                                       (85.1% logic, 14.9% route)

=========================================================================
CPU : 7.19 / 8.55 s | Elapsed : 7.00 / 7.00 s
 
--> 

Total memory usage is 99568 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)