t5b6b.vhd

5b6b编码

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--
-- Title       : enc5b6b
-- Design      : codec5B6B
-- Author      : edamaster
-- Company     : SOHO
--
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--
-- File        : e:\GeNing\hdldesign\activehdl_design\Codec5B6B\src\enc5b6b.vhd
-- Generated   : Mon Jul 22 17:44:14 2002
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {enc5b6b} architecture {enc5b6b}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
--entity enc5b6b is
entity T5b6b is
	 port(
		 reset : in std_logic;
		 clk : in std_logic;
		 din : in std_logic;
		 Pulse1_5 : out std_logic;
		 dout : out std_logic
	     );
  end T5b6b; 
--end enc5b6b;

--}} End of automatically maintained section



---architecture enc5b6b of enc5b6b is 
architecture T5b6b of	T5b6b is 
signal cnt : integer range 0 to 5;
signal encp, en_i : std_logic;		--encode pulse
signal palld : std_logic_vector(4 downto 0);
signal encdat : std_logic_vector(5 downto 0);
signal modeflag : std_logic;
subtype  word  	is std_logic_vector(6 downto 0);
type 	memory		is array ( 0 to 63 ) of word ; 
-- rom flag&encodedata(5:0)
constant  rom	: memory   := ( 
-- negative mode
"0110010", "1100001", "1100010", "0100011", "1100100", "0100101", "0100110", "0000111",
"1101000", "0101001", "0101010", "0001011", "0101100", "1000101", "1000110", "0001110", 
"0110001", "1010001", "1010010", "0010011", "0110100", "0010101", "0010110", "1010100", 
"1011000", "0011001", "0011010", "1001010", "0011100", "1001001", "1001100", "0001101",
-- positive mode
"0110010", "1110011", "1110110", "0100011", "1110101", "0100101", "0100110", "1100111",
"1101011", "0101001", "0101010", "0001011", "0101100", "1101101", "1101110", "0001110",
"0110001", "1111001", "1111010", "0010011", "0110100", "0010101", "0010110", "1010111",
"0111000", "0011001", "0011010", "1011011", "0011100", "1011101", "1011110", "0001101"
					);
begin

	-- enter your statements here --
	
	cnt_proc: process(clk,reset)
	begin
		if rising_edge(clk) then
			if cnt/=5 then
				cnt<=cnt+1;
			else
				cnt<=0;
			end if;
			if cnt=5 then
				en_i<='0';
			else
				en_i<='1';
			end if;
			encp<=not en_i; 
		end if;
		if reset='0' then
			cnt<=0;
		end if;
	end process;
	Pulse1_5<=en_i;				-- en is one clock ahead of real data
	
	s2p_proc: process(clk,reset)
	begin
		if rising_edge(clk) then
			palld<=palld(3 downto 0) & din;
		end if;
		if reset='0' then
			palld<=(others=>'0');
		end if;
	end process;
	
	encode_proc: process(clk,reset)
		variable addr : integer range 0 to 63;
		variable romvalue : std_logic_vector(6 downto 0);
	begin
		if rising_edge(clk) then
			if encp='1' then
				addr:= conv_integer(modeflag & palld);
				romvalue:=rom(addr);
				encdat<=romvalue(5 downto 0);
				if romvalue(6)='1' then	   -- pos/neg mode flip
					modeflag<=not modeflag;			
				end if;
			else
				encdat<=encdat(4 downto 0) & '0';
			end if;
		end if;
		if reset='0' then
			encdat<=(others=>'0');
			modeflag<='0';
		end if;
	end process;
	
	dout<=encdat(5);
				

				

end T5b6b;