scrambler.v

来自「多路并行扰码」· Verilog 代码 · 共 71 行

// Parallel scrambler
//
// xikang
// 2003-6-10
//


module pscrambler( en, reset, clk, clken, datin, datout );
	input reset, clk, clken, en;

`include "scrambler.h"

	// definitions in scrambler.h
	// N : dat bit width
	// L : length of scrambler
	// Ap, Bp, Cp, Dp: used for scrambling
	// A_1p, B_1p, C_1p, D_1p: used for discrambling

	input [1 : N] datin;
	output reg [1 : N] datout;

	reg [1 : L] d;   //state registers
	reg [1 : L] d_tmp;   //state registers
	reg [1 : N] s;   //state registers

	always @ ( posedge clk, negedge reset )
	begin : label_scrambler
		integer i, j;
		reg [1 : L] tmpL;
		reg [1 : N] tmpN;

		if( ! reset )
		begin
			d 		<= 0;
			datout	<= 0;
		end
		else if( clken )
		begin
			d_tmp = 0;
			for( i = 1; i <= L; i = i + 1 )
			begin
				tmpL = Ap[i];
				tmpN = Bp[i];
				for( j = 1; j <= L; j = j + 1 )
					d_tmp[i] = d_tmp[i] ^ ( tmpL[j] & d[j] );

				for( j = 1; j <= N; j = j + 1 )
					d_tmp[i] = d_tmp[i] ^ ( tmpN[j] & datin[j] );
			end
			d		<= d_tmp;

			s = 0;
			for( i = 1; i <= N; i = i + 1 )
			begin
				tmpL = Cp[i];
				tmpN = Dp[i];
				for( j = 1; j <= L; j = j + 1 )
					s[i] = s[i] ^ ( tmpL[j] & d[j] );

				for( j = 1; j <= N; j = j + 1 )
					s[i] = s[i] ^ ( tmpN[j] & datin[j] );
			end

			if( en )
				datout	<= s;
			else
				datout	<= datin;
		end
	end
endmodule