tb.v

来自「多路并行扰码」· Verilog 代码 · 共 48 行

module tb (); 

reg clk, reset;
reg [9 : 0] datin, d1, d2;
wire [9 : 0] datout ;

reg ok;

test U_TEST ( reset, clk, datin, datout );

	always @ ( posedge clk, negedge reset )
	begin
		if( ! reset )
		begin
			datin <= 0;
			ok		<= 1;
		end
		else
		begin
			datin <= datin - 1;
			d1		<= datin;
			d2		<= d1;

			if( d2 == datout )
				ok <= 1;
			else
				ok <= 0;
		end
	end


	always
	begin
		#5 clk = 1;
		#5 clk = 0;
	end

	initial
	begin
		reset = 1;
		#10 reset = 0;
		#80 reset = 1;
	end

endmodule