📄 prev_cmp_sin4.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk4 register register q\[1\] q\[5\] 500.0 MHz Internal " "Info: Clock \"clk4\" Internal fmax is restricted to 500.0 MHz between source register \"q\[1\]\" and destination register \"q\[5\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.333 ns + Longest register register " "Info: + Longest register to register delay is 1.333 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[1\] 1 REG LCFF_X19_Y5_N29 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y5_N29; Fanout = 10; REG Node = 'q\[1\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[1] } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.216 ns) + CELL(0.350 ns) 0.566 ns Add0~86 2 COMB LCCOMB_X19_Y5_N0 2 " "Info: 2: + IC(0.216 ns) + CELL(0.350 ns) = 0.566 ns; Loc. = LCCOMB_X19_Y5_N0; Fanout = 2; COMB Node = 'Add0~86'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.566 ns" { q[1] Add0~86 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.601 ns Add0~90 3 COMB LCCOMB_X19_Y5_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.601 ns; Loc. = LCCOMB_X19_Y5_N2; Fanout = 2; COMB Node = 'Add0~90'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~86 Add0~90 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.636 ns Add0~94 4 COMB LCCOMB_X19_Y5_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.636 ns; Loc. = LCCOMB_X19_Y5_N4; Fanout = 2; COMB Node = 'Add0~94'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~90 Add0~94 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.671 ns Add0~98 5 COMB LCCOMB_X19_Y5_N6 1 " "Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.671 ns; Loc. = LCCOMB_X19_Y5_N6; Fanout = 1; COMB Node = 'Add0~98'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add0~94 Add0~98 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 0.796 ns Add0~101 6 COMB LCCOMB_X19_Y5_N8 1 " "Info: 6: + IC(0.000 ns) + CELL(0.125 ns) = 0.796 ns; Loc. = LCCOMB_X19_Y5_N8; Fanout = 1; COMB Node = 'Add0~101'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { Add0~98 Add0~101 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.053 ns) 1.178 ns q\[5\]~17 7 COMB LCCOMB_X19_Y5_N14 1 " "Info: 7: + IC(0.329 ns) + CELL(0.053 ns) = 1.178 ns; Loc. = LCCOMB_X19_Y5_N14; Fanout = 1; COMB Node = 'q\[5\]~17'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.382 ns" { Add0~101 q[5]~17 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.333 ns q\[5\] 8 REG LCFF_X19_Y5_N15 9 " "Info: 8: + IC(0.000 ns) + CELL(0.155 ns) = 1.333 ns; Loc. = LCFF_X19_Y5_N15; Fanout = 9; REG Node = 'q\[5\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { q[5]~17 q[5] } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.788 ns ( 59.11 % ) " "Info: Total cell delay = 0.788 ns ( 59.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.545 ns ( 40.89 % ) " "Info: Total interconnect delay = 0.545 ns ( 40.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { q[1] Add0~86 Add0~90 Add0~94 Add0~98 Add0~101 q[5]~17 q[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "1.333 ns" { q[1] {} Add0~86 {} Add0~90 {} Add0~94 {} Add0~98 {} Add0~101 {} q[5]~17 {} q[5] {} } { 0.000ns 0.216ns 0.000ns 0.000ns 0.000ns 0.000ns 0.329ns 0.000ns } { 0.000ns 0.350ns 0.035ns 0.035ns 0.035ns 0.125ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4 destination 2.463 ns + Shortest register " "Info: + Shortest clock path from clock \"clk4\" to destination register is 2.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk4 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk4'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk4 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk4~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk4~clkctrl'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk4 clk4~clkctrl } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.618 ns) 2.463 ns q\[5\] 3 REG LCFF_X19_Y5_N15 9 " "Info: 3: + IC(0.648 ns) + CELL(0.618 ns) = 2.463 ns; Loc. = LCFF_X19_Y5_N15; Fanout = 9; REG Node = 'q\[5\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { clk4~clkctrl q[5] } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.76 % ) " "Info: Total cell delay = 1.472 ns ( 59.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 40.24 % ) " "Info: Total interconnect delay = 0.991 ns ( 40.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk4 clk4~clkctrl q[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} q[5] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4 source 2.463 ns - Longest register " "Info: - Longest clock path from clock \"clk4\" to source register is 2.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk4 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk4'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk4 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk4~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk4~clkctrl'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk4 clk4~clkctrl } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.618 ns) 2.463 ns q\[1\] 3 REG LCFF_X19_Y5_N29 10 " "Info: 3: + IC(0.648 ns) + CELL(0.618 ns) = 2.463 ns; Loc. = LCFF_X19_Y5_N29; Fanout = 10; REG Node = 'q\[1\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { clk4~clkctrl q[1] } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.76 % ) " "Info: Total cell delay = 1.472 ns ( 59.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 40.24 % ) " "Info: Total interconnect delay = 0.991 ns ( 40.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk4 clk4~clkctrl q[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} q[1] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk4 clk4~clkctrl q[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} q[5] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk4 clk4~clkctrl q[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} q[1] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { q[1] Add0~86 Add0~90 Add0~94 Add0~98 Add0~101 q[5]~17 q[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "1.333 ns" { q[1] {} Add0~86 {} Add0~90 {} Add0~94 {} Add0~98 {} Add0~101 {} q[5]~17 {} q[5] {} } { 0.000ns 0.216ns 0.000ns 0.000ns 0.000ns 0.000ns 0.329ns 0.000ns } { 0.000ns 0.350ns 0.035ns 0.035ns 0.035ns 0.125ns 0.053ns 0.155ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk4 clk4~clkctrl q[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} q[5] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk4 clk4~clkctrl q[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} q[1] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { q[5] {} } { } { } "" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk4 dd4\[5\] q\[3\] 7.054 ns register " "Info: tco from clock \"clk4\" to destination pin \"dd4\[5\]\" through register \"q\[3\]\" is 7.054 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4 source 2.463 ns + Longest register " "Info: + Longest clock path from clock \"clk4\" to source register is 2.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk4 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk4'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk4 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk4~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk4~clkctrl'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk4 clk4~clkctrl } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.618 ns) 2.463 ns q\[3\] 3 REG LCFF_X19_Y5_N31 10 " "Info: 3: + IC(0.648 ns) + CELL(0.618 ns) = 2.463 ns; Loc. = LCFF_X19_Y5_N31; Fanout = 10; REG Node = 'q\[3\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { clk4~clkctrl q[3] } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.76 % ) " "Info: Total cell delay = 1.472 ns ( 59.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 40.24 % ) " "Info: Total interconnect delay = 0.991 ns ( 40.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk4 clk4~clkctrl q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} q[3] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.497 ns + Longest register pin " "Info: + Longest register to pin delay is 4.497 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[3\] 1 REG LCFF_X19_Y5_N31 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y5_N31; Fanout = 10; REG Node = 'q\[3\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[3] } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.378 ns) 1.055 ns Mux2~149 2 COMB LCCOMB_X21_Y5_N20 1 " "Info: 2: + IC(0.677 ns) + CELL(0.378 ns) = 1.055 ns; Loc. = LCCOMB_X21_Y5_N20; Fanout = 1; COMB Node = 'Mux2~149'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.055 ns" { q[3] Mux2~149 } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.288 ns) + CELL(2.154 ns) 4.497 ns dd4\[5\] 3 PIN PIN_U1 0 " "Info: 3: + IC(1.288 ns) + CELL(2.154 ns) = 4.497 ns; Loc. = PIN_U1; Fanout = 0; PIN Node = 'dd4\[5\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.442 ns" { Mux2~149 dd4[5] } "NODE_NAME" } } { "sin4.vhd" "" { Text "E:/AAXIAOLI/boxingsheji/sin4.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.532 ns ( 56.30 % ) " "Info: Total cell delay = 2.532 ns ( 56.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.965 ns ( 43.70 % ) " "Info: Total interconnect delay = 1.965 ns ( 43.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.497 ns" { q[3] Mux2~149 dd4[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.497 ns" { q[3] {} Mux2~149 {} dd4[5] {} } { 0.000ns 0.677ns 1.288ns } { 0.000ns 0.378ns 2.154ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk4 clk4~clkctrl q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk4 {} clk4~combout {} clk4~clkctrl {} q[3] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.497 ns" { q[3] Mux2~149 dd4[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.497 ns" { q[3] {} Mux2~149 {} dd4[5] {} } { 0.000ns 0.677ns 1.288ns } { 0.000ns 0.378ns 2.154ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 16 00:43:23 2008 " "Info: Processing ended: Wed Apr 16 00:43:23 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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