sin4.map.rpt

用modelsim仿真一个正弦波产生程序

; HDL message level                                                           ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                             ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                    ; 100                ; 100                ;
; Clock MUX Protection                                                        ; On                 ; On                 ;
; Block Design Naming                                                         ; Auto               ; Auto               ;
+-----------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                              ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; sin4.vhd                         ; yes             ; User VHDL File  ; E:/AAXIAOLI/boxing/sin4.vhd  ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 19    ;
; Dedicated logic registers                     ; 6     ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 6     ;
;                                               ;       ;
; Total combinational functions                 ; 19    ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 0     ;
;     -- 6 input functions                      ; 8     ;
;     -- 5 input functions                      ; 0     ;
;     -- 4 input functions                      ; 0     ;
;     -- <=3 input functions                    ; 11    ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 14    ;
;     -- extended LUT mode                      ; 0     ;
;     -- arithmetic mode                        ; 5     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 25    ;
;                                               ;       ;
; Total registers                               ; 6     ;
;     -- Dedicated logic registers              ; 6     ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 13    ;
;                                               ;       ;
; I/O pins                                      ; 9     ;
; Maximum fan-out node                          ; q[0]  ;
; Maximum fan-out                               ; 10    ;
; Total fan-out                                 ; 84    ;
; Average fan-out                               ; 2.47  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |sin4                      ; 19 (19)           ; 6 (6)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 9    ; 0            ; |sin4               ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 6     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; q[0]                                   ; 10      ;
; q[1]                                   ; 9       ;
; q[2]                                   ; 9       ;
; q[3]                                   ; 9       ;
; q[4]                                   ; 9       ;
; q[5]                                   ; 9       ;
; Total number of inverted registers = 6 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Apr 16 01:10:49 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin4 -c sin4
Info: Found 2 design units, including 1 entities, in source file sin4.vhd
    Info: Found design unit 1: sin4-dacc
    Info: Found entity 1: sin4
Info: Elaborating entity "sin4" for the top level hierarchy
Info: Implemented 28 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 8 output pins
    Info: Implemented 19 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 154 megabytes of memory during processing
    Info: Processing ended: Wed Apr 16 01:10:52 2008
    Info: Elapsed time: 00:00:03