sin4.vhd

用modelsim仿真一个正弦波产生程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sin4 is
port(clk4,reset:in std_logic;
dd4:out integer range 255 downto 0);
end;
architecture dacc of sin4 is
signal q: integer range 63 downto 0;
begin
process(clk4,reset)
begin
    if(reset='1')then q<=00; 
    elsif (clk4'event and clk4='1') 
    then
q<=q+1;
end if;
end process;
process(q)
begin
case q is
when 00=>dd4<=255;
when 01=>dd4<=254;
when 02=>dd4<=253;
when 03=>dd4<=250;
when 04=>dd4<=245;
when 05=>dd4<=240;
when 06=>dd4<=234;
when 07=>dd4<=226;
when 08=>dd4<=218;
when 09=>dd4<=208;
when 10=>dd4<=198;
when 11=>dd4<=188;
when 12=>dd4<=176;
when 13=>dd4<=165;
when 14=>dd4<=152;
when 15=>dd4<=140;
when 16=>dd4<=128;
when 17=>dd4<=115;
when 18=>dd4<=103;
when 19=>dd4<=90;
when 20=>dd4<=79;
when 21=>dd4<=67;
when 22=>dd4<=57;
when 23=>dd4<=47;
when 24=>dd4<=37;
when 25=>dd4<=29;
when 26=>dd4<=21;
when 27=>dd4<=15;
when 28=>dd4<=10;
when 29=>dd4<=5;
when 30=>dd4<=2;
when 31=>dd4<=1;
when 32=>dd4<=0;
when 33=>dd4<=1;
when 34=>dd4<=2;
when 35=>dd4<=5;
when 36=>dd4<=10;
when 37=>dd4<=15;
when 38=>dd4<=21;
when 39=>dd4<=29;
when 40=>dd4<=37;
when 41=>dd4<=47;
when 42=>dd4<=57;
when 43=>dd4<=67;
when 44=>dd4<=79;
when 45=>dd4<=90;
when 46=>dd4<=103;
when 47=>dd4<=115;
when 48=>dd4<=128;
when 49=>dd4<=140;
when 50=>dd4<=165;
when 51=>dd4<=176;
when 52=>dd4<=188;
when 53=>dd4<=198;
when 54=>dd4<=208;
when 55=>dd4<=218;
when 56=>dd4<=226;
when 57=>dd4<=234;
when 58=>dd4<=240;
when 59=>dd4<=245;
when 60=>dd4<=250;
when 61=>dd4<=253;
when 62=>dd4<=254;
when 63=>dd4<=255;
when others=>null;
end case;
end process;
end architecture;