sin4.tan.rpt

用modelsim仿真一个正弦波产生程序

; tco                                                            ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To     ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A   ; None         ; 7.054 ns   ; q[3] ; dd4[5] ; clk4       ;
; N/A   ; None         ; 7.034 ns   ; q[3] ; dd4[2] ; clk4       ;
; N/A   ; None         ; 6.986 ns   ; q[0] ; dd4[5] ; clk4       ;
; N/A   ; None         ; 6.951 ns   ; q[0] ; dd4[2] ; clk4       ;
; N/A   ; None         ; 6.910 ns   ; q[4] ; dd4[5] ; clk4       ;
; N/A   ; None         ; 6.906 ns   ; q[0] ; dd4[1] ; clk4       ;
; N/A   ; None         ; 6.876 ns   ; q[2] ; dd4[5] ; clk4       ;
; N/A   ; None         ; 6.875 ns   ; q[4] ; dd4[2] ; clk4       ;
; N/A   ; None         ; 6.860 ns   ; q[2] ; dd4[2] ; clk4       ;
; N/A   ; None         ; 6.800 ns   ; q[1] ; dd4[1] ; clk4       ;
; N/A   ; None         ; 6.765 ns   ; q[5] ; dd4[5] ; clk4       ;
; N/A   ; None         ; 6.761 ns   ; q[5] ; dd4[1] ; clk4       ;
; N/A   ; None         ; 6.735 ns   ; q[5] ; dd4[2] ; clk4       ;
; N/A   ; None         ; 6.634 ns   ; q[1] ; dd4[5] ; clk4       ;
; N/A   ; None         ; 6.604 ns   ; q[1] ; dd4[2] ; clk4       ;
; N/A   ; None         ; 6.579 ns   ; q[2] ; dd4[1] ; clk4       ;
; N/A   ; None         ; 6.534 ns   ; q[4] ; dd4[1] ; clk4       ;
; N/A   ; None         ; 6.481 ns   ; q[3] ; dd4[1] ; clk4       ;
; N/A   ; None         ; 6.387 ns   ; q[3] ; dd4[6] ; clk4       ;
; N/A   ; None         ; 6.371 ns   ; q[3] ; dd4[4] ; clk4       ;
; N/A   ; None         ; 6.369 ns   ; q[3] ; dd4[7] ; clk4       ;
; N/A   ; None         ; 6.360 ns   ; q[3] ; dd4[3] ; clk4       ;
; N/A   ; None         ; 6.307 ns   ; q[0] ; dd4[6] ; clk4       ;
; N/A   ; None         ; 6.301 ns   ; q[0] ; dd4[7] ; clk4       ;
; N/A   ; None         ; 6.297 ns   ; q[0] ; dd4[4] ; clk4       ;
; N/A   ; None         ; 6.288 ns   ; q[0] ; dd4[3] ; clk4       ;
; N/A   ; None         ; 6.276 ns   ; q[0] ; dd4[0] ; clk4       ;
; N/A   ; None         ; 6.231 ns   ; q[4] ; dd4[6] ; clk4       ;
; N/A   ; None         ; 6.224 ns   ; q[4] ; dd4[7] ; clk4       ;
; N/A   ; None         ; 6.221 ns   ; q[4] ; dd4[4] ; clk4       ;
; N/A   ; None         ; 6.212 ns   ; q[2] ; dd4[6] ; clk4       ;
; N/A   ; None         ; 6.212 ns   ; q[4] ; dd4[3] ; clk4       ;
; N/A   ; None         ; 6.194 ns   ; q[2] ; dd4[4] ; clk4       ;
; N/A   ; None         ; 6.188 ns   ; q[2] ; dd4[7] ; clk4       ;
; N/A   ; None         ; 6.183 ns   ; q[2] ; dd4[3] ; clk4       ;
; N/A   ; None         ; 6.171 ns   ; q[1] ; dd4[0] ; clk4       ;
; N/A   ; None         ; 6.132 ns   ; q[5] ; dd4[0] ; clk4       ;
; N/A   ; None         ; 6.089 ns   ; q[5] ; dd4[6] ; clk4       ;
; N/A   ; None         ; 6.080 ns   ; q[5] ; dd4[7] ; clk4       ;
; N/A   ; None         ; 6.076 ns   ; q[5] ; dd4[4] ; clk4       ;
; N/A   ; None         ; 6.068 ns   ; q[5] ; dd4[3] ; clk4       ;
; N/A   ; None         ; 5.956 ns   ; q[1] ; dd4[6] ; clk4       ;
; N/A   ; None         ; 5.953 ns   ; q[2] ; dd4[0] ; clk4       ;
; N/A   ; None         ; 5.950 ns   ; q[1] ; dd4[7] ; clk4       ;
; N/A   ; None         ; 5.946 ns   ; q[1] ; dd4[4] ; clk4       ;
; N/A   ; None         ; 5.937 ns   ; q[1] ; dd4[3] ; clk4       ;
; N/A   ; None         ; 5.904 ns   ; q[4] ; dd4[0] ; clk4       ;
; N/A   ; None         ; 5.847 ns   ; q[3] ; dd4[0] ; clk4       ;
+-------+--------------+------------+------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Apr 16 01:11:19 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sin4 -c sin4 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk4" is an undefined clock
Info: Clock "clk4" Internal fmax is restricted to 500.0 MHz between source register "q[1]" and destination register "q[5]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.333 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y5_N29; Fanout = 10; REG Node = 'q[1]'
            Info: 2: + IC(0.216 ns) + CELL(0.350 ns) = 0.566 ns; Loc. = LCCOMB_X19_Y5_N0; Fanout = 2; COMB Node = 'Add0~86'
            Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.601 ns; Loc. = LCCOMB_X19_Y5_N2; Fanout = 2; COMB Node = 'Add0~90'
            Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.636 ns; Loc. = LCCOMB_X19_Y5_N4; Fanout = 2; COMB Node = 'Add0~94'
            Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.671 ns; Loc. = LCCOMB_X19_Y5_N6; Fanout = 1; COMB Node = 'Add0~98'
            Info: 6: + IC(0.000 ns) + CELL(0.125 ns) = 0.796 ns; Loc. = LCCOMB_X19_Y5_N8; Fanout = 1; COMB Node = 'Add0~101'
            Info: 7: + IC(0.329 ns) + CELL(0.053 ns) = 1.178 ns; Loc. = LCCOMB_X19_Y5_N14; Fanout = 1; COMB Node = 'q[5]~17'
            Info: 8: + IC(0.000 ns) + CELL(0.155 ns) = 1.333 ns; Loc. = LCFF_X19_Y5_N15; Fanout = 9; REG Node = 'q[5]'
            Info: Total cell delay = 0.788 ns ( 59.11 % )
            Info: Total interconnect delay = 0.545 ns ( 40.89 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk4" to destination register is 2.463 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk4'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk4~clkctrl'
                Info: 3: + IC(0.648 ns) + CELL(0.618 ns) = 2.463 ns; Loc. = LCFF_X19_Y5_N15; Fanout = 9; REG Node = 'q[5]'
                Info: Total cell delay = 1.472 ns ( 59.76 % )
                Info: Total interconnect delay = 0.991 ns ( 40.24 % )
            Info: - Longest clock path from clock "clk4" to source register is 2.463 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk4'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk4~clkctrl'
                Info: 3: + IC(0.648 ns) + CELL(0.618 ns) = 2.463 ns; Loc. = LCFF_X19_Y5_N29; Fanout = 10; REG Node = 'q[1]'
                Info: Total cell delay = 1.472 ns ( 59.76 % )
                Info: Total interconnect delay = 0.991 ns ( 40.24 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tco from clock "clk4" to destination pin "dd4[5]" through register "q[3]" is 7.054 ns
    Info: + Longest clock path from clock "clk4" to source register is 2.463 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk4'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk4~clkctrl'
        Info: 3: + IC(0.648 ns) + CELL(0.618 ns) = 2.463 ns; Loc. = LCFF_X19_Y5_N31; Fanout = 10; REG Node = 'q[3]'
        Info: Total cell delay = 1.472 ns ( 59.76 % )
        Info: Total interconnect delay = 0.991 ns ( 40.24 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 4.497 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y5_N31; Fanout = 10; REG Node = 'q[3]'
        Info: 2: + IC(0.677 ns) + CELL(0.378 ns) = 1.055 ns; Loc. = LCCOMB_X21_Y5_N20; Fanout = 1; COMB Node = 'Mux2~149'
        Info: 3: + IC(1.288 ns) + CELL(2.154 ns) = 4.497 ns; Loc. = PIN_U1; Fanout = 0; PIN Node = 'dd4[5]'
        Info: Total cell delay = 2.532 ns ( 56.30 % )
        Info: Total interconnect delay = 1.965 ns ( 43.70 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 115 megabytes of memory during processing
    Info: Processing ended: Wed Apr 16 01:11:21 2008
    Info: Elapsed time: 00:00:02