vga_addr.v

来自「用来实现VGA发生时序」· Verilog 代码 · 共 22 行

module vga_vaddr(clk,rst,Hgate,Vgate,vaddr);
	input clk;
	input rst;
	input Hgate;
	input Vgate;
	
	output [18:0] vaddr;
	reg [18:0] vaddr;
	
	always @(posedge clk)
		if (rst)
			vaddr = 19'b0;
		else if (Vgate)
				begin
					if (Hgate)vaddr = vaddr + 1;
				end
			else vaddr = 0;
	
endmodule