vga.map.eqn

用来实现VGA发生时序

--B2_cnt_len[6] is vga_vtim:ver_gen|cnt_len[6]
--operation mode is normal

B2_cnt_len[6]_lut_out = B2_cnt_len[6] & (B2L04 # B2L201 & B2L74) # !B2_cnt_len[6] & B2L201 & B2L74;
B2_cnt_len[6] = DFFEA(B2_cnt_len[6]_lut_out, clk, VCC, , , , );


--B2_cnt[5] is vga_vtim:ver_gen|cnt[5]
--operation mode is normal

B2_cnt[5]_lut_out = B2_cnt[5] & (B2L04 # B2L76 & B2L34) # !B2_cnt[5] & B2L76 & B2L34;
B2_cnt[5] = DFFEA(B2_cnt[5]_lut_out, clk, VCC, , , , );


--B1_cnt[5] is vga_vtim:hor_gen|cnt[5]
--operation mode is normal

B1_cnt[5]_lut_out = B1_cnt[5] & (B1L16 # B1L27 & B1L34) # !B1_cnt[5] & B1L27 & B1L34;
B1_cnt[5] = DFFEA(B1_cnt[5]_lut_out, clk, VCC, , , , );


--B1_cnt_len[5] is vga_vtim:hor_gen|cnt_len[5]
--operation mode is normal

B1_cnt_len[5]_lut_out = B1_cnt_len[5] & (B1L16 # B1L501 & B1L84) # !B1_cnt_len[5] & B1L501 & B1L84;
B1_cnt_len[5] = DFFEA(B1_cnt_len[5]_lut_out, clk, VCC, , , , );


--B2_cnt_len[5] is vga_vtim:ver_gen|cnt_len[5]
--operation mode is normal

B2_cnt_len[5]_lut_out = B2_cnt_len[5] & (B2L04 # B2L001 & B2L74) # !B2_cnt_len[5] & B2L001 & B2L74;
B2_cnt_len[5] = DFFEA(B2_cnt_len[5]_lut_out, clk, VCC, , , , );


--B2_cnt[4] is vga_vtim:ver_gen|cnt[4]
--operation mode is normal

B2_cnt[4]_lut_out = B2_cnt[4] & (B2L04 # B2L56 & B2L34) # !B2_cnt[4] & B2L56 & B2L34;
B2_cnt[4] = DFFEA(B2_cnt[4]_lut_out, clk, VCC, , , , );


--B1_cnt[4] is vga_vtim:hor_gen|cnt[4]
--operation mode is normal

B1_cnt[4]_lut_out = B1_cnt[4] & (B1L16 # B1L07 & B1L34) # !B1_cnt[4] & B1L07 & B1L34;
B1_cnt[4] = DFFEA(B1_cnt[4]_lut_out, clk, VCC, , , , );


--B1_cnt_len[4] is vga_vtim:hor_gen|cnt_len[4]
--operation mode is normal

B1_cnt_len[4]_lut_out = !rst & (B1L15 # B1L301 & B1L94);
B1_cnt_len[4] = DFFEA(B1_cnt_len[4]_lut_out, clk, VCC, , , , );


--B2_cnt_len[4] is vga_vtim:ver_gen|cnt_len[4]
--operation mode is normal

B2_cnt_len[4]_lut_out = B2L94 # B2_cnt_len[4] & B2L04 # !B2L05;
B2_cnt_len[4] = DFFEA(B2_cnt_len[4]_lut_out, clk, VCC, , , , );


--B2_cnt[3] is vga_vtim:ver_gen|cnt[3]
--operation mode is normal

B2_cnt[3]_lut_out = B2L64 # B2L54 # B2_cnt[3] & B2L04;
B2_cnt[3] = DFFEA(B2_cnt[3]_lut_out, clk, VCC, , , , );


--B1_cnt[3] is vga_vtim:hor_gen|cnt[3]
--operation mode is normal

B1_cnt[3]_lut_out = B1L74 # B1L54 # B1_cnt[3] & B1L16;
B1_cnt[3] = DFFEA(B1_cnt[3]_lut_out, clk, VCC, , , , );


--B1L05 is vga_vtim:hor_gen|i235~195
--operation mode is normal

B1L05 = B1L731Q & clk_ena & (B1L301 # B1L721);


--B1L15 is vga_vtim:hor_gen|i235~196
--operation mode is normal

B1L15 = B1L05 # clk_ena & !B1L331Q # !clk_ena & B1_cnt_len[4];


--B1_cnt_len[3] is vga_vtim:hor_gen|cnt_len[3]
--operation mode is normal

B1_cnt_len[3]_lut_out = !rst & (B1L35 # B1L101 & B1L94);
B1_cnt_len[3] = DFFEA(B1_cnt_len[3]_lut_out, clk, VCC, , , , );


--B2L94 is vga_vtim:ver_gen|i235~189
--operation mode is normal

B2L94 = B2L89 & B2L84 & (B2L231Q # B2L321);


--B2L05 is vga_vtim:ver_gen|i235~190
--operation mode is normal

B2L05 = B2L821Q & (B2L221 # !B2L231Q) # !B2L84;


--B2_cnt_len[3] is vga_vtim:ver_gen|cnt_len[3]
--operation mode is normal

B2_cnt_len[3]_lut_out = B2_cnt_len[3] & (B2L04 # B2L69 & B2L74) # !B2_cnt_len[3] & B2L69 & B2L74;
B2_cnt_len[3] = DFFEA(B2_cnt_len[3]_lut_out, clk, VCC, , , , );


--B2L64 is vga_vtim:ver_gen|i220~193
--operation mode is normal

B2L64 = B2L36 & B2L84 & (B2L14 # !B2L35);


--B2_cnt[2] is vga_vtim:ver_gen|cnt[2]
--operation mode is normal

B2_cnt[2]_lut_out = B2_cnt[2] & (B2L04 # B2L16 & B2L34) # !B2_cnt[2] & B2L16 & B2L34;
B2_cnt[2] = DFFEA(B2_cnt[2]_lut_out, clk, VCC, , , , );


--B1L74 is vga_vtim:hor_gen|i220~113
--operation mode is normal

B1L74 = B1L86 & B1L64 & (B1L24 # !B1L75);


--B1_cnt[2] is vga_vtim:hor_gen|cnt[2]
--operation mode is normal

B1_cnt[2]_lut_out = B1_cnt[2] & (B1L16 # B1L66 & B1L34) # !B1_cnt[2] & B1L66 & B1L34;
B1_cnt[2] = DFFEA(B1_cnt[2]_lut_out, clk, VCC, , , , );


--B1L25 is vga_vtim:hor_gen|i236~190
--operation mode is normal

B1L25 = B1L731Q & clk_ena & (B1L101 # B1L721);


--B1L35 is vga_vtim:hor_gen|i236~191
--operation mode is normal

B1L35 = B1L25 # clk_ena & !B1L331Q # !clk_ena & B1_cnt_len[3];


--B1_cnt_len[2] is vga_vtim:hor_gen|cnt_len[2]
--operation mode is normal

B1_cnt_len[2]_lut_out = B1_cnt_len[2] & (B1L16 # B1L99 & B1L84) # !B1_cnt_len[2] & B1L99 & B1L84;
B1_cnt_len[2] = DFFEA(B1_cnt_len[2]_lut_out, clk, VCC, , , , );


--B2_cnt_len[2] is vga_vtim:ver_gen|cnt_len[2]
--operation mode is normal

B2_cnt_len[2]_lut_out = B2L15 # B2_cnt_len[2] & B2L04 # !B2L05;
B2_cnt_len[2] = DFFEA(B2_cnt_len[2]_lut_out, clk, VCC, , , , );


--B2_cnt[1] is vga_vtim:ver_gen|cnt[1]
--operation mode is normal

B2_cnt[1]_lut_out = !rst & (i4 & B2L721 # !i4 & B2_cnt[1]);
B2_cnt[1] = DFFEA(B2_cnt[1]_lut_out, clk, VCC, , , , );


--B1_cnt[1] is vga_vtim:hor_gen|cnt[1]
--operation mode is normal

B1_cnt[1]_lut_out = !rst & (clk_ena & B1L231 # !clk_ena & B1_cnt[1]);
B1_cnt[1] = DFFEA(B1_cnt[1]_lut_out, clk, VCC, , , , );


--B1_cnt_len[1] is vga_vtim:hor_gen|cnt_len[1]
--operation mode is normal

B1_cnt_len[1]_lut_out = B1_cnt_len[1] & (B1L16 # B1L79 & B1L84) # !B1_cnt_len[1] & B1L79 & B1L84;
B1_cnt_len[1] = DFFEA(B1_cnt_len[1]_lut_out, clk, VCC, , , , );


--B2L15 is vga_vtim:ver_gen|i237~178
--operation mode is normal

B2L15 = B2L49 & B2L84 & (B2L231Q # B2L321);


--B2_cnt_len[1] is vga_vtim:ver_gen|cnt_len[1]
--operation mode is normal

B2_cnt_len[1]_lut_out = B2L25 # B2_cnt_len[1] & B2L04 # !B2L05;
B2_cnt_len[1] = DFFEA(B2_cnt_len[1]_lut_out, clk, VCC, , , , );


--B2L621 is vga_vtim:ver_gen|i~624
--operation mode is normal

B2L621 = B2L95 & (B2L131Q # B2L231Q) # !B2L521;


--B2L721 is vga_vtim:ver_gen|i~625
--operation mode is normal

B2L721 = B2L621 # !B2L421 & (B2L95 # !B2L98);


--B2_cnt[0] is vga_vtim:ver_gen|cnt[0]
--operation mode is normal

B2_cnt[0]_lut_out = B2_cnt[0] & (B2L04 # B2L75 & B2L34) # !B2_cnt[0] & B2L75 & B2L34;
B2_cnt[0] = DFFEA(B2_cnt[0]_lut_out, clk, VCC, , , , );


--B1L131 is vga_vtim:hor_gen|i~593
--operation mode is normal

B1L131 = B1L46 & (B1L731Q # B1L631Q) # !B1L821;


--B1L231 is vga_vtim:hor_gen|i~594
--operation mode is normal

B1L231 = B1L131 # !B1L921 & (B1L46 # !B1L49);


--B1_cnt[0] is vga_vtim:hor_gen|cnt[0]
--operation mode is normal

B1_cnt[0]_lut_out = B1_cnt[0] & (B1L16 # B1L26 & B1L34) # !B1_cnt[0] & B1L26 & B1L34;
B1_cnt[0] = DFFEA(B1_cnt[0]_lut_out, clk, VCC, , , , );


--B1_cnt_len[0] is vga_vtim:hor_gen|cnt_len[0]
--operation mode is normal

B1_cnt_len[0]_lut_out = !rst & (B1L55 # B1L59 & B1L94);
B1_cnt_len[0] = DFFEA(B1_cnt_len[0]_lut_out, clk, VCC, , , , );


--B2L25 is vga_vtim:ver_gen|i238~178
--operation mode is normal

B2L25 = B2L29 & B2L84 & (B2L231Q # B2L321);


--B2_cnt_len[0] is vga_vtim:ver_gen|cnt_len[0]
--operation mode is normal

B2_cnt_len[0]_lut_out = B2_cnt_len[0] & (B2L04 # B2L09 & B2L74) # !B2_cnt_len[0] & B2L09 & B2L74;
B2_cnt_len[0] = DFFEA(B2_cnt_len[0]_lut_out, clk, VCC, , , , );


--B1L45 is vga_vtim:hor_gen|i239~190
--operation mode is normal

B1L45 = B1L731Q & clk_ena & (B1L721 # B1L59);


--B1L55 is vga_vtim:hor_gen|i239~191
--operation mode is normal

B1L55 = B1L45 # clk_ena & !B1L331Q # !clk_ena & B1_cnt_len[0];


--B2L65 is vga_vtim:ver_gen|i241~190
--operation mode is normal

B2L65 = B1L1Q & clk_ena & !B2L231Q;


--B2L44 is vga_vtim:ver_gen|i220~191
--operation mode is normal

B2L44 = B1L1Q & clk_ena & !B2L98 & !rst;


--B1L44 is vga_vtim:hor_gen|i220~109
--operation mode is normal

B1L44 = clk_ena & !rst & !B1L49;


--B1L54 is vga_vtim:hor_gen|i220~111
--operation mode is normal

B1L54 = clk_ena & !rst & !B1L49 & B1L531Q;


--B1L95 is vga_vtim:hor_gen|i241~118
--operation mode is normal

B1L95 = B1L531Q # B1L431Q # B1L06 # !B1L331Q;


--B1L821 is vga_vtim:hor_gen|i~590
--operation mode is normal

B1L821 = B1L331Q & (!B1L721 # !B1L731Q);


--B1L65 is vga_vtim:hor_gen|i240~137
--operation mode is normal

B1L65 = clk_ena & !rst & !B1L821;


--B2L93 is vga_vtim:ver_gen|i205~109
--operation mode is normal

B2L93 = !rst & (B2L98 # !clk_ena # !B1L1Q);


--B2L84 is vga_vtim:ver_gen|i235~188
--operation mode is normal

B2L84 = B1L1Q & clk_ena & !rst;


--B2L321 is vga_vtim:ver_gen|i~621
--operation mode is normal

B2L321 = B2L031Q # B2L921Q # B2L131Q;


--B2L73 is vga_vtim:ver_gen|i200~50
--operation mode is normal

B2L73 = B2L98 & (B2L031Q # B2L921Q # B2L131Q);


--B1L83 is vga_vtim:hor_gen|i200~35
--operation mode is normal

B1L83 = B1L49 & (B1L531Q # B1L431Q # B1L631Q);


--B2L24 is vga_vtim:ver_gen|i209~193
--operation mode is normal

B2L24 = B2L131Q # B2L98 & (B2L031Q # B2L921Q);


--B2L04 is vga_vtim:ver_gen|i208~187
--operation mode is normal

B2L04 = !rst & (!clk_ena # !B1L1Q);


--B1L14 is vga_vtim:hor_gen|i208~99
--operation mode is normal

B1L14 = B1L49 & (B1L531Q # B1L431Q);


--B1L94 is vga_vtim:hor_gen|i235~194
--operation mode is normal

B1L94 = clk_ena & (B1L531Q # B1L431Q # B1L631Q);


--rst is rst
--operation mode is input

rst = INPUT();


--clk_ena is clk_ena
--operation mode is input

clk_ena = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--enab is enab
--operation mode is output

enab = OUTPUT(i6);


--hsync is hsync
--operation mode is output

hsync = OUTPUT(B1L3Q);


--vsync is vsync
--operation mode is output

vsync = OUTPUT(B2L2Q);


--vgate is vgate
--operation mode is output

vgate = OUTPUT(B2L1Q);


--vaddr[18] is vaddr[18]
--operation mode is output

vaddr[18] = OUTPUT(E1_safe_q[18]);


--vaddr[17] is vaddr[17]
--operation mode is output

vaddr[17] = OUTPUT(E1_safe_q[17]);


--vaddr[16] is vaddr[16]
--operation mode is output

vaddr[16] = OUTPUT(E1_safe_q[16]);


--vaddr[15] is vaddr[15]
--operation mode is output

vaddr[15] = OUTPUT(E1_safe_q[15]);


--vaddr[14] is vaddr[14]
--operation mode is output

vaddr[14] = OUTPUT(E1_safe_q[14]);


--vaddr[13] is vaddr[13]
--operation mode is output

vaddr[13] = OUTPUT(E1_safe_q[13]);


--vaddr[12] is vaddr[12]
--operation mode is output

vaddr[12] = OUTPUT(E1_safe_q[12]);


--vaddr[11] is vaddr[11]
--operation mode is output

vaddr[11] = OUTPUT(E1_safe_q[11]);


--vaddr[10] is vaddr[10]
--operation mode is output

vaddr[10] = OUTPUT(E1_safe_q[10]);


--vaddr[9] is vaddr[9]
--operation mode is output

vaddr[9] = OUTPUT(E1_safe_q[9]);


--vaddr[8] is vaddr[8]
--operation mode is output

vaddr[8] = OUTPUT(E1_safe_q[8]);


--vaddr[7] is vaddr[7]
--operation mode is output

vaddr[7] = OUTPUT(E1_safe_q[7]);


--vaddr[6] is vaddr[6]
--operation mode is output

vaddr[6] = OUTPUT(E1_safe_q[6]);


--vaddr[5] is vaddr[5]
--operation mode is output

vaddr[5] = OUTPUT(E1_safe_q[5]);


--vaddr[4] is vaddr[4]
--operation mode is output

vaddr[4] = OUTPUT(E1_safe_q[4]);


--vaddr[3] is vaddr[3]
--operation mode is output

vaddr[3] = OUTPUT(E1_safe_q[3]);


--vaddr[2] is vaddr[2]
--operation mode is output

vaddr[2] = OUTPUT(E1_safe_q[2]);


--vaddr[1] is vaddr[1]
--operation mode is output

vaddr[1] = OUTPUT(E1_safe_q[1]);


--vaddr[0] is vaddr[0]
--operation mode is output

vaddr[0] = OUTPUT(E1_safe_q[0]);