vga.map.eqn

用来实现VGA发生时序

--B2L1Q is vga_vtim:ver_gen|Gate~reg0
--operation mode is normal

B2L1Q_lut_out = B2L54 # !C1L1 & (!B2L55 # !B2L65);
B2L1Q = DFFEA(B2L1Q_lut_out, clk, VCC, , , , );


--B1L2Q is vga_vtim:hor_gen|Gate~reg0
--operation mode is normal

B1L2Q_lut_out = B1L54 # B1L2Q & B1L95 & !rst;
B1L2Q = DFFEA(B1L2Q_lut_out, clk, VCC, , , , );


--i6 is i6
--operation mode is normal

i6 = B2L1Q & B1L2Q;


--B1L3Q is vga_vtim:hor_gen|Sync~reg0
--operation mode is normal

B1L3Q_lut_out = B1L65 # B1L3Q & B1L85 & !rst;
B1L3Q = DFFEA(B1L3Q_lut_out, clk, VCC, , , , );


--B2L2Q is vga_vtim:ver_gen|Sync~reg0
--operation mode is normal

B2L2Q_lut_out = B2L45 # i4 & !B2L521 & !rst;
B2L2Q = DFFEA(B2L2Q_lut_out, clk, VCC, , , , );


--C1L1 is vga_vaddr:vramaddr_gen|i43~9
--operation mode is normal

C1L1 = rst # !B2L1Q;


--B1L1Q is vga_vtim:hor_gen|Done~reg0
--operation mode is normal

B1L1Q_lut_out = !rst & (clk_ena & B1L031 # !clk_ena & B1L1Q);
B1L1Q = DFFEA(B1L1Q_lut_out, clk, VCC, , , , );


--i4 is i4
--operation mode is normal

i4 = B1L1Q & clk_ena;


--B2L231Q is vga_vtim:ver_gen|state~14
--operation mode is normal

B2L231Q_lut_out = B2L83 # B2L131Q & B2L44;
B2L231Q = DFFEA(B2L231Q_lut_out, clk, VCC, , , , );


--B2L031Q is vga_vtim:ver_gen|state~12
--operation mode is normal

B2L031Q_lut_out = B2L031Q & (B2L93 # B2L921Q & B2L44) # !B2L031Q & B2L921Q & B2L44;
B2L031Q = DFFEA(B2L031Q_lut_out, clk, VCC, , , , );


--B2L54 is vga_vtim:ver_gen|i220~192
--operation mode is normal

B2L54 = B2L031Q & B2L44;


--B2L131Q is vga_vtim:ver_gen|state~13
--operation mode is normal

B2L131Q_lut_out = B2L031Q & (B2L44 # B2L131Q & B2L93) # !B2L031Q & B2L131Q & B2L93;
B2L131Q = DFFEA(B2L131Q_lut_out, clk, VCC, , , , );


--B2L921Q is vga_vtim:ver_gen|state~11
--operation mode is normal

B2L921Q_lut_out = B2L921Q & (B2L93 # B2L84 & !B2L521) # !B2L921Q & B2L84 & !B2L521;
B2L921Q = DFFEA(B2L921Q_lut_out, clk, VCC, , , , );


--B2L421 is vga_vtim:ver_gen|i~622
--operation mode is normal

B2L421 = !B2L031Q & !B2L921Q;


--B2L821Q is vga_vtim:ver_gen|state~10
--operation mode is normal

B2L821Q_lut_out = !rst & (B2L821Q # !B2L73 & i4);
B2L821Q = DFFEA(B2L821Q_lut_out, clk, VCC, , , , );


--B2L55 is vga_vtim:ver_gen|i241~187
--operation mode is normal

B2L55 = B2L421 & B2L821Q & (!B2L98 # !B2L131Q);


--B1L531Q is vga_vtim:hor_gen|state~12
--operation mode is normal

B1L531Q_lut_out = B1L531Q & (B1L04 # B1L431Q & B1L44) # !B1L531Q & B1L431Q & B1L44;
B1L531Q = DFFEA(B1L531Q_lut_out, clk, VCC, , , , );


--B1L64 is vga_vtim:hor_gen|i220~112
--operation mode is normal

B1L64 = clk_ena & !rst;


--B1L731Q is vga_vtim:hor_gen|state~14
--operation mode is normal

B1L731Q_lut_out = B1L93 # B1L631Q & B1L44;
B1L731Q = DFFEA(B1L731Q_lut_out, clk, VCC, , , , );


--B1L631Q is vga_vtim:hor_gen|state~13
--operation mode is normal

B1L631Q_lut_out = B1L54 # B1L631Q & B1L04;
B1L631Q = DFFEA(B1L631Q_lut_out, clk, VCC, , , , );


--B1L06 is vga_vtim:hor_gen|i241~119
--operation mode is normal

B1L06 = B1L731Q # B1L631Q & B1L49 # !clk_ena;


--B1L331Q is vga_vtim:hor_gen|state~10
--operation mode is normal

B1L331Q_lut_out = !rst & (B1L331Q # !B1L83 & clk_ena);
B1L331Q = DFFEA(B1L331Q_lut_out, clk, VCC, , , , );


--B1L431Q is vga_vtim:hor_gen|state~11
--operation mode is normal

B1L431Q_lut_out = B1L65 # B1L431Q & B1L04;
B1L431Q = DFFEA(B1L431Q_lut_out, clk, VCC, , , , );


--B1L921 is vga_vtim:hor_gen|i~591
--operation mode is normal

B1L921 = !B1L531Q & !B1L431Q;


--B1L031 is vga_vtim:hor_gen|i~592
--operation mode is normal

B1L031 = B1L731Q & B1L721;


--B1L75 is vga_vtim:hor_gen|i240~140
--operation mode is normal

B1L75 = !B1L531Q & !B1L631Q & (!B1L49 # !B1L431Q);


--B1L85 is vga_vtim:hor_gen|i240~141
--operation mode is normal

B1L85 = B1L731Q # !clk_ena # !B1L75;


--B2L35 is vga_vtim:ver_gen|i240~221
--operation mode is normal

B2L35 = !B2L031Q & !B2L131Q & (!B2L98 # !B2L921Q);


--B2L45 is vga_vtim:ver_gen|i240~222
--operation mode is normal

B2L45 = B2L2Q & !rst & (!B2L35 # !B2L65);


--B2L521 is vga_vtim:ver_gen|i~623
--operation mode is normal

B2L521 = B2L821Q & (B2L221 # !B2L231Q);


--B2L83 is vga_vtim:ver_gen|i203~118
--operation mode is normal

B2L83 = B2L231Q & !rst & (B2L221 # !i4);


--B1L04 is vga_vtim:hor_gen|i206~93
--operation mode is normal

B1L04 = !rst & (B1L49 # !clk_ena);


--B1L93 is vga_vtim:hor_gen|i203~70
--operation mode is normal

B1L93 = B1L731Q & !rst & (!clk_ena # !B1L721);


--B2_cnt[15] is vga_vtim:ver_gen|cnt[15]
--operation mode is normal

B2_cnt[15]_lut_out = B2_cnt[15] & (B2L04 # B2L78 & B2L34) # !B2_cnt[15] & B2L78 & B2L34;
B2_cnt[15] = DFFEA(B2_cnt[15]_lut_out, clk, VCC, , , , );


--B1_cnt[15] is vga_vtim:hor_gen|cnt[15]
--operation mode is normal

B1_cnt[15]_lut_out = B1_cnt[15] & (B1L16 # B1L29 & B1L34) # !B1_cnt[15] & B1L29 & B1L34;
B1_cnt[15] = DFFEA(B1_cnt[15]_lut_out, clk, VCC, , , , );


--B1_cnt_len[15] is vga_vtim:hor_gen|cnt_len[15]
--operation mode is normal

B1_cnt_len[15]_lut_out = B1_cnt_len[15] & (B1L16 # B1L521 & B1L84) # !B1_cnt_len[15] & B1L521 & B1L84;
B1_cnt_len[15] = DFFEA(B1_cnt_len[15]_lut_out, clk, VCC, , , , );


--B2_cnt_len[15] is vga_vtim:ver_gen|cnt_len[15]
--operation mode is normal

B2_cnt_len[15]_lut_out = B2_cnt_len[15] & (B2L04 # B2L021 & B2L74) # !B2_cnt_len[15] & B2L021 & B2L74;
B2_cnt_len[15] = DFFEA(B2_cnt_len[15]_lut_out, clk, VCC, , , , );


--B2L14 is vga_vtim:ver_gen|i208~188
--operation mode is normal

B2L14 = B2L231Q & B2L221;


--B2L34 is vga_vtim:ver_gen|i209~194
--operation mode is normal

B2L34 = i4 & !rst & (B2L24 # B2L14);


--B2_cnt[14] is vga_vtim:ver_gen|cnt[14]
--operation mode is normal

B2_cnt[14]_lut_out = B2_cnt[14] & (B2L04 # B2L58 & B2L34) # !B2_cnt[14] & B2L58 & B2L34;
B2_cnt[14] = DFFEA(B2_cnt[14]_lut_out, clk, VCC, , , , );


--B1L24 is vga_vtim:hor_gen|i208~100
--operation mode is normal

B1L24 = B1L731Q & !B1L721;


--B1L34 is vga_vtim:hor_gen|i209~106
--operation mode is normal

B1L34 = B1L64 & (B1L631Q # B1L24 # B1L14);


--B1L16 is vga_vtim:hor_gen|i242~8
--operation mode is normal

B1L16 = !clk_ena & !rst;


--B1_cnt[14] is vga_vtim:hor_gen|cnt[14]
--operation mode is normal

B1_cnt[14]_lut_out = B1_cnt[14] & (B1L16 # B1L09 & B1L34) # !B1_cnt[14] & B1L09 & B1L34;
B1_cnt[14] = DFFEA(B1_cnt[14]_lut_out, clk, VCC, , , , );


--B1L84 is vga_vtim:hor_gen|i224~108
--operation mode is normal

B1L84 = B1L64 & (B1L631Q # B1L24 # !B1L921);


--B1_cnt_len[14] is vga_vtim:hor_gen|cnt_len[14]
--operation mode is normal

B1_cnt_len[14]_lut_out = B1_cnt_len[14] & (B1L16 # B1L321 & B1L84) # !B1_cnt_len[14] & B1L321 & B1L84;
B1_cnt_len[14] = DFFEA(B1_cnt_len[14]_lut_out, clk, VCC, , , , );


--B2L74 is vga_vtim:ver_gen|i224~132
--operation mode is normal

B2L74 = i4 & !rst & (B2L14 # B2L321);


--B2_cnt_len[14] is vga_vtim:ver_gen|cnt_len[14]
--operation mode is normal

B2_cnt_len[14]_lut_out = B2_cnt_len[14] & (B2L04 # B2L811 & B2L74) # !B2_cnt_len[14] & B2L811 & B2L74;
B2_cnt_len[14] = DFFEA(B2_cnt_len[14]_lut_out, clk, VCC, , , , );


--B2_cnt[13] is vga_vtim:ver_gen|cnt[13]
--operation mode is normal

B2_cnt[13]_lut_out = B2_cnt[13] & (B2L04 # B2L38 & B2L34) # !B2_cnt[13] & B2L38 & B2L34;
B2_cnt[13] = DFFEA(B2_cnt[13]_lut_out, clk, VCC, , , , );


--B1_cnt[13] is vga_vtim:hor_gen|cnt[13]
--operation mode is normal

B1_cnt[13]_lut_out = B1_cnt[13] & (B1L16 # B1L88 & B1L34) # !B1_cnt[13] & B1L88 & B1L34;
B1_cnt[13] = DFFEA(B1_cnt[13]_lut_out, clk, VCC, , , , );


--B1_cnt_len[13] is vga_vtim:hor_gen|cnt_len[13]
--operation mode is normal

B1_cnt_len[13]_lut_out = B1_cnt_len[13] & (B1L16 # B1L121 & B1L84) # !B1_cnt_len[13] & B1L121 & B1L84;
B1_cnt_len[13] = DFFEA(B1_cnt_len[13]_lut_out, clk, VCC, , , , );


--B2_cnt_len[13] is vga_vtim:ver_gen|cnt_len[13]
--operation mode is normal

B2_cnt_len[13]_lut_out = B2_cnt_len[13] & (B2L04 # B2L611 & B2L74) # !B2_cnt_len[13] & B2L611 & B2L74;
B2_cnt_len[13] = DFFEA(B2_cnt_len[13]_lut_out, clk, VCC, , , , );


--B2_cnt[12] is vga_vtim:ver_gen|cnt[12]
--operation mode is normal

B2_cnt[12]_lut_out = B2_cnt[12] & (B2L04 # B2L18 & B2L34) # !B2_cnt[12] & B2L18 & B2L34;
B2_cnt[12] = DFFEA(B2_cnt[12]_lut_out, clk, VCC, , , , );


--B1_cnt[12] is vga_vtim:hor_gen|cnt[12]
--operation mode is normal

B1_cnt[12]_lut_out = B1_cnt[12] & (B1L16 # B1L68 & B1L34) # !B1_cnt[12] & B1L68 & B1L34;
B1_cnt[12] = DFFEA(B1_cnt[12]_lut_out, clk, VCC, , , , );


--B1_cnt_len[12] is vga_vtim:hor_gen|cnt_len[12]
--operation mode is normal

B1_cnt_len[12]_lut_out = B1_cnt_len[12] & (B1L16 # B1L911 & B1L84) # !B1_cnt_len[12] & B1L911 & B1L84;
B1_cnt_len[12] = DFFEA(B1_cnt_len[12]_lut_out, clk, VCC, , , , );


--B2_cnt_len[12] is vga_vtim:ver_gen|cnt_len[12]
--operation mode is normal

B2_cnt_len[12]_lut_out = B2_cnt_len[12] & (B2L04 # B2L411 & B2L74) # !B2_cnt_len[12] & B2L411 & B2L74;
B2_cnt_len[12] = DFFEA(B2_cnt_len[12]_lut_out, clk, VCC, , , , );


--B2_cnt[11] is vga_vtim:ver_gen|cnt[11]
--operation mode is normal

B2_cnt[11]_lut_out = B2_cnt[11] & (B2L04 # B2L97 & B2L34) # !B2_cnt[11] & B2L97 & B2L34;
B2_cnt[11] = DFFEA(B2_cnt[11]_lut_out, clk, VCC, , , , );


--B1_cnt[11] is vga_vtim:hor_gen|cnt[11]
--operation mode is normal

B1_cnt[11]_lut_out = B1_cnt[11] & (B1L16 # B1L48 & B1L34) # !B1_cnt[11] & B1L48 & B1L34;
B1_cnt[11] = DFFEA(B1_cnt[11]_lut_out, clk, VCC, , , , );


--B1_cnt_len[11] is vga_vtim:hor_gen|cnt_len[11]
--operation mode is normal

B1_cnt_len[11]_lut_out = B1_cnt_len[11] & (B1L16 # B1L711 & B1L84) # !B1_cnt_len[11] & B1L711 & B1L84;
B1_cnt_len[11] = DFFEA(B1_cnt_len[11]_lut_out, clk, VCC, , , , );


--B2_cnt_len[11] is vga_vtim:ver_gen|cnt_len[11]
--operation mode is normal

B2_cnt_len[11]_lut_out = B2_cnt_len[11] & (B2L04 # B2L211 & B2L74) # !B2_cnt_len[11] & B2L211 & B2L74;
B2_cnt_len[11] = DFFEA(B2_cnt_len[11]_lut_out, clk, VCC, , , , );


--B2_cnt[10] is vga_vtim:ver_gen|cnt[10]
--operation mode is normal

B2_cnt[10]_lut_out = B2_cnt[10] & (B2L04 # B2L77 & B2L34) # !B2_cnt[10] & B2L77 & B2L34;
B2_cnt[10] = DFFEA(B2_cnt[10]_lut_out, clk, VCC, , , , );


--B1_cnt[10] is vga_vtim:hor_gen|cnt[10]
--operation mode is normal

B1_cnt[10]_lut_out = B1_cnt[10] & (B1L16 # B1L28 & B1L34) # !B1_cnt[10] & B1L28 & B1L34;
B1_cnt[10] = DFFEA(B1_cnt[10]_lut_out, clk, VCC, , , , );


--B1_cnt_len[10] is vga_vtim:hor_gen|cnt_len[10]
--operation mode is normal

B1_cnt_len[10]_lut_out = B1_cnt_len[10] & (B1L16 # B1L511 & B1L84) # !B1_cnt_len[10] & B1L511 & B1L84;
B1_cnt_len[10] = DFFEA(B1_cnt_len[10]_lut_out, clk, VCC, , , , );


--B2_cnt_len[10] is vga_vtim:ver_gen|cnt_len[10]
--operation mode is normal

B2_cnt_len[10]_lut_out = B2_cnt_len[10] & (B2L04 # B2L011 & B2L74) # !B2_cnt_len[10] & B2L011 & B2L74;
B2_cnt_len[10] = DFFEA(B2_cnt_len[10]_lut_out, clk, VCC, , , , );


--B2_cnt[9] is vga_vtim:ver_gen|cnt[9]
--operation mode is normal

B2_cnt[9]_lut_out = B2_cnt[9] & (B2L04 # B2L57 & B2L34) # !B2_cnt[9] & B2L57 & B2L34;
B2_cnt[9] = DFFEA(B2_cnt[9]_lut_out, clk, VCC, , , , );


--B1_cnt[9] is vga_vtim:hor_gen|cnt[9]
--operation mode is normal

B1_cnt[9]_lut_out = B1_cnt[9] & (B1L16 # B1L08 & B1L34) # !B1_cnt[9] & B1L08 & B1L34;
B1_cnt[9] = DFFEA(B1_cnt[9]_lut_out, clk, VCC, , , , );


--B1_cnt_len[9] is vga_vtim:hor_gen|cnt_len[9]
--operation mode is normal

B1_cnt_len[9]_lut_out = B1_cnt_len[9] & (B1L16 # B1L311 & B1L84) # !B1_cnt_len[9] & B1L311 & B1L84;
B1_cnt_len[9] = DFFEA(B1_cnt_len[9]_lut_out, clk, VCC, , , , );


--B2_cnt_len[9] is vga_vtim:ver_gen|cnt_len[9]
--operation mode is normal

B2_cnt_len[9]_lut_out = B2_cnt_len[9] & (B2L04 # B2L801 & B2L74) # !B2_cnt_len[9] & B2L801 & B2L74;
B2_cnt_len[9] = DFFEA(B2_cnt_len[9]_lut_out, clk, VCC, , , , );


--B2_cnt[8] is vga_vtim:ver_gen|cnt[8]
--operation mode is normal

B2_cnt[8]_lut_out = B2_cnt[8] & (B2L04 # B2L37 & B2L34) # !B2_cnt[8] & B2L37 & B2L34;
B2_cnt[8] = DFFEA(B2_cnt[8]_lut_out, clk, VCC, , , , );


--B1_cnt[8] is vga_vtim:hor_gen|cnt[8]
--operation mode is normal

B1_cnt[8]_lut_out = B1_cnt[8] & (B1L16 # B1L87 & B1L34) # !B1_cnt[8] & B1L87 & B1L34;
B1_cnt[8] = DFFEA(B1_cnt[8]_lut_out, clk, VCC, , , , );


--B1_cnt_len[8] is vga_vtim:hor_gen|cnt_len[8]
--operation mode is normal

B1_cnt_len[8]_lut_out = B1_cnt_len[8] & (B1L16 # B1L111 & B1L84) # !B1_cnt_len[8] & B1L111 & B1L84;
B1_cnt_len[8] = DFFEA(B1_cnt_len[8]_lut_out, clk, VCC, , , , );


--B2_cnt_len[8] is vga_vtim:ver_gen|cnt_len[8]
--operation mode is normal

B2_cnt_len[8]_lut_out = B2_cnt_len[8] & (B2L04 # B2L601 & B2L74) # !B2_cnt_len[8] & B2L601 & B2L74;
B2_cnt_len[8] = DFFEA(B2_cnt_len[8]_lut_out, clk, VCC, , , , );


--B2_cnt[7] is vga_vtim:ver_gen|cnt[7]
--operation mode is normal

B2_cnt[7]_lut_out = B2_cnt[7] & (B2L04 # B2L17 & B2L34) # !B2_cnt[7] & B2L17 & B2L34;
B2_cnt[7] = DFFEA(B2_cnt[7]_lut_out, clk, VCC, , , , );


--B1_cnt[7] is vga_vtim:hor_gen|cnt[7]
--operation mode is normal

B1_cnt[7]_lut_out = B1_cnt[7] & (B1L16 # B1L67 & B1L34) # !B1_cnt[7] & B1L67 & B1L34;
B1_cnt[7] = DFFEA(B1_cnt[7]_lut_out, clk, VCC, , , , );


--B1_cnt_len[7] is vga_vtim:hor_gen|cnt_len[7]
--operation mode is normal

B1_cnt_len[7]_lut_out = B1_cnt_len[7] & (B1L16 # B1L901 & B1L84) # !B1_cnt_len[7] & B1L901 & B1L84;
B1_cnt_len[7] = DFFEA(B1_cnt_len[7]_lut_out, clk, VCC, , , , );


--B2_cnt_len[7] is vga_vtim:ver_gen|cnt_len[7]
--operation mode is normal

B2_cnt_len[7]_lut_out = B2_cnt_len[7] & (B2L04 # B2L401 & B2L74) # !B2_cnt_len[7] & B2L401 & B2L74;
B2_cnt_len[7] = DFFEA(B2_cnt_len[7]_lut_out, clk, VCC, , , , );


--B2_cnt[6] is vga_vtim:ver_gen|cnt[6]
--operation mode is normal

B2_cnt[6]_lut_out = B2_cnt[6] & (B2L04 # B2L96 & B2L34) # !B2_cnt[6] & B2L96 & B2L34;
B2_cnt[6] = DFFEA(B2_cnt[6]_lut_out, clk, VCC, , , , );


--B1_cnt[6] is vga_vtim:hor_gen|cnt[6]
--operation mode is normal

B1_cnt[6]_lut_out = B1_cnt[6] & (B1L16 # B1L47 & B1L34) # !B1_cnt[6] & B1L47 & B1L34;
B1_cnt[6] = DFFEA(B1_cnt[6]_lut_out, clk, VCC, , , , );


--B1_cnt_len[6] is vga_vtim:hor_gen|cnt_len[6]
--operation mode is normal

B1_cnt_len[6]_lut_out = B1_cnt_len[6] & (B1L16 # B1L701 & B1L84) # !B1_cnt_len[6] & B1L701 & B1L84;
B1_cnt_len[6] = DFFEA(B1_cnt_len[6]_lut_out, clk, VCC, , , , );