📄 vga.map.rpt
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; Analysis & Synthesis Resource Utilization by Entity ;
+-----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
; |VGA ; 195 (2) ; 98 ; 0 ; 26 ; 0 ; 97 (2) ; 3 (0) ; 95 (0) ; 87 (0) ; 0 (0) ; |VGA ; work ;
; |vga_vaddr:vramaddr_gen| ; 20 (20) ; 19 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 19 (19) ; 19 (19) ; 0 (0) ; |VGA|vga_vaddr:vramaddr_gen ; work ;
; |vga_vtim:hor_gen| ; 85 (85) ; 40 ; 0 ; 0 ; 0 ; 45 (45) ; 2 (2) ; 38 (38) ; 34 (34) ; 0 (0) ; |VGA|vga_vtim:hor_gen ; work ;
; |vga_vtim:ver_gen| ; 88 (88) ; 39 ; 0 ; 0 ; 0 ; 49 (49) ; 1 (1) ; 38 (38) ; 34 (34) ; 0 (0) ; |VGA|vga_vtim:ver_gen ; work ;
+-----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------------------------+
; State Machine - |VGA|vga_vtim:ver_gen|state ;
+------------------+-----------------+------------------+------------------+------------------+------------------+
; Name ; state.len_state ; state.gate_state ; state.gdel_state ; state.sync_state ; state.idle_state ;
+------------------+-----------------+------------------+------------------+------------------+------------------+
; state.idle_state ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state.gate_state ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state.gdel_state ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state.sync_state ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state.len_state ; 1 ; 0 ; 0 ; 0 ; 1 ;
+------------------+-----------------+------------------+------------------+------------------+------------------+
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------------------------+
; State Machine - |VGA|vga_vtim:hor_gen|state ;
+------------------+-----------------+------------------+------------------+------------------+------------------+
; Name ; state.len_state ; state.gate_state ; state.gdel_state ; state.sync_state ; state.idle_state ;
+------------------+-----------------+------------------+------------------+------------------+------------------+
; state.idle_state ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state.gate_state ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state.gdel_state ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state.sync_state ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state.len_state ; 1 ; 0 ; 0 ; 0 ; 1 ;
+------------------+-----------------+------------------+------------------+------------------+------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 98 ;
; Number of registers using Synchronous Clear ; 54 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 68 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; 3:1 ; 19 bits ; 38 LEs ; 19 LEs ; 19 LEs ; Yes ; |VGA|vga_vaddr:vramaddr_gen|vaddr[1] ;
; 3:1 ; 13 bits ; 26 LEs ; 13 LEs ; 13 LEs ; Yes ; |VGA|vga_vtim:hor_gen|cnt_len[6] ;
; 3:1 ; 13 bits ; 26 LEs ; 13 LEs ; 13 LEs ; Yes ; |VGA|vga_vtim:ver_gen|cnt_len[6] ;
; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |VGA|vga_vtim:ver_gen|cnt_len[2] ;
; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |VGA|vga_vtim:hor_gen|cnt_len[3] ;
; 8:1 ; 15 bits ; 75 LEs ; 30 LEs ; 45 LEs ; Yes ; |VGA|vga_vtim:ver_gen|cnt[9] ;
; 8:1 ; 15 bits ; 75 LEs ; 30 LEs ; 45 LEs ; Yes ; |VGA|vga_vtim:hor_gen|cnt[4] ;
; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |VGA|vga_vtim:ver_gen|state~22 ;
; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |VGA|vga_vtim:hor_gen|state~21 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: vga_vtim:hor_gen ;
+----------------+-------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------+
; Tsync ; 2 ; Signed Integer ;
; Tgdel ; 2 ; Signed Integer ;
; Tgate ; 10 ; Signed Integer ;
; Tlen ; 25 ; Signed Integer ;
; idle_state ; 00001 ; Unsigned Binary ;
; sync_state ; 00010 ; Unsigned Binary ;
; gdel_state ; 00100 ; Unsigned Binary ;
; gate_state ; 01000 ; Unsigned Binary ;
; len_state ; 10000 ; Unsigned Binary ;
+----------------+-------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: vga_vtim:ver_gen ;
+----------------+-------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------+
; Tsync ; 2 ; Signed Integer ;
; Tgdel ; 2 ; Signed Integer ;
; Tgate ; 10 ; Signed Integer ;
; Tlen ; 22 ; Signed Integer ;
; idle_state ; 00001 ; Unsigned Binary ;
; sync_state ; 00010 ; Unsigned Binary ;
; gdel_state ; 00100 ; Unsigned Binary ;
; gate_state ; 01000 ; Unsigned Binary ;
; len_state ; 10000 ; Unsigned Binary ;
+----------------+-------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Tue Dec 11 15:17:22 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA
Info: Found 1 design units, including 1 entities, in source file vga_tgen.v
Info: Found entity 1: VGA
Info: Found 1 design units, including 1 entities, in source file vga_vtim.v
Info: Found entity 1: vga_vtim
Info: Found 1 design units, including 1 entities, in source file vga_addr.v
Info: Found entity 1: vga_vaddr
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
Info: Found entity 1: Block1
Info: Elaborating entity "VGA" for the top level hierarchy
Info: Elaborating entity "vga_vtim" for hierarchy "vga_vtim:hor_gen"
Info: Elaborating entity "vga_vtim" for hierarchy "vga_vtim:ver_gen"
Info: Elaborating entity "vga_vaddr" for hierarchy "vga_vaddr:vramaddr_gen"
Warning (10230): Verilog HDL assignment warning at vga_addr.v(16): truncated value with size 32 to match size of target (19)
Info: State machine "|VGA|vga_vtim:ver_gen|state" contains 5 states
Info: State machine "|VGA|vga_vtim:hor_gen|state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|VGA|vga_vtim:ver_gen|state"
Info: Encoding result for state machine "|VGA|vga_vtim:ver_gen|state"
Info: Completed encoding using 5 state bits
Info: Encoded state bit "vga_vtim:ver_gen|state.len_state"
Info: Encoded state bit "vga_vtim:ver_gen|state.gate_state"
Info: Encoded state bit "vga_vtim:ver_gen|state.gdel_state"
Info: Encoded state bit "vga_vtim:ver_gen|state.sync_state"
Info: Encoded state bit "vga_vtim:ver_gen|state.idle_state"
Info: State "|VGA|vga_vtim:ver_gen|state.idle_state" uses code string "00000"
Info: State "|VGA|vga_vtim:ver_gen|state.gate_state" uses code string "01001"
Info: State "|VGA|vga_vtim:ver_gen|state.gdel_state" uses code string "00101"
Info: State "|VGA|vga_vtim:ver_gen|state.sync_state" uses code string "00011"
Info: State "|VGA|vga_vtim:ver_gen|state.len_state" uses code string "10001"
Info: Selected Auto state machine encoding method for state machine "|VGA|vga_vtim:hor_gen|state"
Info: Encoding result for state machine "|VGA|vga_vtim:hor_gen|state"
Info: Completed encoding using 5 state bits
Info: Encoded state bit "vga_vtim:hor_gen|state.len_state"
Info: Encoded state bit "vga_vtim:hor_gen|state.gate_state"
Info: Encoded state bit "vga_vtim:hor_gen|state.gdel_state"
Info: Encoded state bit "vga_vtim:hor_gen|state.sync_state"
Info: Encoded state bit "vga_vtim:hor_gen|state.idle_state"
Info: State "|VGA|vga_vtim:hor_gen|state.idle_state" uses code string "00000"
Info: State "|VGA|vga_vtim:hor_gen|state.gate_state" uses code string "01001"
Info: State "|VGA|vga_vtim:hor_gen|state.gdel_state" uses code string "00101"
Info: State "|VGA|vga_vtim:hor_gen|state.sync_state" uses code string "00011"
Info: State "|VGA|vga_vtim:hor_gen|state.len_state" uses code string "10001"
Info: Implemented 221 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 23 output pins
Info: Implemented 195 logic cells
Info: Generated suppressed messages file D:/alteraprj/VGA/VGA.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 136 megabytes of memory during processing
Info: Processing ended: Tue Dec 11 15:17:27 2007
Info: Elapsed time: 00:00:05
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/alteraprj/VGA/VGA.map.smsg.
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