vga.drc.rpt

用来实现VGA发生时序

; Rule T102: Top nodes with the highest number of fan-outs         ; clk                                  ; 98      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; rst                                  ; 84      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|state.idle_state    ; 34      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|state.idle_state    ; 34      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Done~295            ; 33      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|cnt_len[6]~841      ; 31      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|state.len_state     ; 20      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Add1~274            ; 19      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|state.len_state     ; 19      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vaddr:vramaddr_gen|vaddr[1]~223  ; 19      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Add1~274            ; 18      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|cnt[9]~1139         ; 15      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|cnt[4]~1139         ; 15      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; clk_ena                              ; 13      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Add0~275            ; 8       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Add0~275            ; 8       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Done                ; 6       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Gate                ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Add1~293            ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Add1~303            ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vaddr:vramaddr_gen|vaddr[3]~207  ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Add1~303            ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Add1~293            ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Add0~304            ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Add0~294            ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Add0~304            ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Add0~294            ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vaddr:vramaddr_gen|vaddr[13]~217 ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vaddr:vramaddr_gen|vaddr[8]~212  ; 5       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|state.gate_state    ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Add1~283            ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Add1~283            ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Gate                ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Add0~284            ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|state.gate_state    ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Add0~284            ; 4       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|state.gdel_state    ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|cnt_len[2]~842      ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|cnt_len[3]~1044     ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|state.sync_state    ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|state.gdel_state    ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|Sync                ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vclk_ena                             ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:ver_gen|state.sync_state    ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Sync                ; 3       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vaddr:vramaddr_gen|vaddr[8]      ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vaddr:vramaddr_gen|vaddr[2]      ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vaddr:vramaddr_gen|vaddr[4]      ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vaddr:vramaddr_gen|vaddr[3]      ; 2       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; vga_vtim:hor_gen|Selector17~85       ; 2       ;
+------------------------------------------------------------------+--------------------------------------+---------+


+---------------------------+
; Design Assistant Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Design Assistant
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Tue Dec 11 15:17:50 2007
Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off VGA -c VGA
Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 6 node(s) with highest fan-out.
    Info: Node "rst" has 84 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Done~295" has 33 fan-out(s)
    Info: Node "vga_vtim:ver_gen|state.idle_state" has 34 fan-out(s)
    Info: Node "vga_vtim:ver_gen|cnt_len[6]~841" has 31 fan-out(s)
    Info: Node "vga_vtim:hor_gen|state.idle_state" has 34 fan-out(s)
    Info: Node "clk" has 98 fan-out(s)
Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.
    Info: Node "clk" has 98 fan-out(s)
    Info: Node "rst" has 84 fan-out(s)
    Info: Node "vga_vtim:ver_gen|state.idle_state" has 34 fan-out(s)
    Info: Node "vga_vtim:hor_gen|state.idle_state" has 34 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Done~295" has 33 fan-out(s)
    Info: Node "vga_vtim:ver_gen|cnt_len[6]~841" has 31 fan-out(s)
    Info: Node "vga_vtim:hor_gen|state.len_state" has 20 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Add1~274" has 19 fan-out(s)
    Info: Node "vga_vtim:ver_gen|state.len_state" has 19 fan-out(s)
    Info: Node "vga_vaddr:vramaddr_gen|vaddr[1]~223" has 19 fan-out(s)
    Info: Node "vga_vtim:ver_gen|Add1~274" has 18 fan-out(s)
    Info: Node "vga_vtim:ver_gen|cnt[9]~1139" has 15 fan-out(s)
    Info: Node "vga_vtim:hor_gen|cnt[4]~1139" has 15 fan-out(s)
    Info: Node "clk_ena" has 13 fan-out(s)
    Info: Node "vga_vtim:ver_gen|Add0~275" has 8 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Add0~275" has 8 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Done" has 6 fan-out(s)
    Info: Node "vga_vtim:ver_gen|Gate" has 5 fan-out(s)
    Info: Node "vga_vtim:ver_gen|Add1~293" has 5 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Add1~303" has 5 fan-out(s)
    Info: Node "vga_vaddr:vramaddr_gen|vaddr[3]~207" has 5 fan-out(s)
    Info: Node "vga_vtim:ver_gen|Add1~303" has 5 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Add1~293" has 5 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Add0~304" has 5 fan-out(s)
    Info: Node "vga_vtim:hor_gen|Add0~294" has 5 fan-out(s)
    Info: Node "vga_vtim:ver_gen|Add0~304" has 5 fan-out(s)
    Info: Node "vga_vtim:ver_gen|Add0~294" has 5 fan-out(s)
    Info: Node "vga_vaddr:vramaddr_gen|vaddr[13]~217" has 5 fan-out(s)
    Info: Node "vga_vaddr:vramaddr_gen|vaddr[8]~212" has 5 fan-out(s)
    Info: Node "vga_vtim:hor_gen|state.gate_state" has 4 fan-out(s)
    Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info: Design Assistant information: finished post-fitting analysis of current design -- generated 56 information messages and 0 warning messages
Info: Quartus II Design Assistant was successful. 0 errors, 0 warnings
    Info: Allocated 94 megabytes of memory during processing
    Info: Processing ended: Tue Dec 11 15:17:52 2007
    Info: Elapsed time: 00:00:02