📄 vga.drc.rpt
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Design Assistant report for VGA
Tue Dec 11 15:17:52 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Design Assistant Summary
3. Design Assistant Settings
4. Information only Violations
5. Design Assistant Messages
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; Legal Notice ;
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Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; Design Assistant Summary ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status ; Analyzed - Tue Dec 11 15:17:52 2007 ;
; Revision Name ; VGA ;
; Top-level Entity Name ; VGA ;
; Family ; Cyclone ;
; Total Critical Violations ; 0 ;
; Total High Violations ; 0 ;
; Total Medium Violations ; 0 ;
; Total Information only Violations ; 56 ;
+-----------------------------------+-------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Option ; Setting ; To ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Design Assistant mode ; Post-Fitting ; ;
; Threshold value for clock net not mapped to clock spines rule ; 25 ; ;
; Minimum number of node fan-out ; 30 ; ;
; Maximum number of nodes to report ; 50 ; ;
; Rule C101: Gated clock should be implemented according to the Altera standard scheme ; On ; ;
; Rule C102: Logic cell should not be used to generate inverted clock ; On ; ;
; Rule C103: Gated clock is not feeding at least a pre-defined number of clock port to effectively save power ; On ; ;
; Rule C104: Clock signal source should drive only input clock ports ; On ; ;
; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On ; ;
; Rule C106: Clock signal source should not drive registers that are triggered by different clock edges ; On ; ;
; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ;
; Rule R102: External reset should be synchronized using two cascaded registers ; On ; ;
; Rule R103: External reset should be correctly synchronized ; On ; ;
; Rule R104: The reset signal that is generated in one clock domain and is used in the other clock domain, should be correctly synchronized ; On ; ;
; Rule R105: The reset signal that is generated in one clock domain and is used in the other clock domain, should be synchronized ; On ; ;
; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ;
; Rule T102: Top nodes with the highest number of fan-outs ; On ; ;
; Rule A101: Design should not contain combinational loops ; On ; ;
; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ;
; Rule A103: Design should not contain delay chains ; On ; ;
; Rule A104: Design should not contain ripple clock structures ; On ; ;
; Rule A105: Pulses should not be implemented asynchronously ; On ; ;
; Rule A106: Multiple pulses should not be generated in design ; On ; ;
; Rule A107: Design should not contain SR latches ; On ; ;
; Rule A108: Design should not contain latches ; On ; ;
; Rule A109: Combinational logic should not directly drive write enable signal of asynchronous RAM ; On ; ;
; Rule A110: Design should not contain asynchronous memory ; On ; ;
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ;
; Rule S103: More than one asynchronous signal port of the same register should not be driven by the same signal source ; On ; ;
; Rule S104: Clock port and any other signal port of same register should not be driven by the same signal source ; On ; ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ;
; Rule H101: Only one VREF pin should be assigned to the HardCopy test pin in an I/O bank (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ; ;
; Rule H102: PLL clock output drives multiple clock network types (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ; ;
; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains ; Off ; ;
; Rule M102: No reset signal defined to initialize the state machine ; Off ; ;
; Rule M103: State machine should not contain an unreachable state ; Off ; ;
; Rule M104: State machine should not contain a deadlock state ; Off ; ;
; Rule M105: State machine should not contain a dead transition ; Off ; ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
+-------------------------------------------------------------------------------------------------------------------+
; Information only Violations ;
+------------------------------------------------------------------+--------------------------------------+---------+
; Rule name ; Name ; Fan-Out ;
+------------------------------------------------------------------+--------------------------------------+---------+
; Rule T101: Nodes with more than the specified number of fan-outs ; rst ; 84 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; vga_vtim:hor_gen|Done~295 ; 33 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; vga_vtim:ver_gen|state.idle_state ; 34 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; vga_vtim:ver_gen|cnt_len[6]~841 ; 31 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; vga_vtim:hor_gen|state.idle_state ; 34 ;
; Rule T101: Nodes with more than the specified number of fan-outs ; clk ; 98 ;
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