lpm_fifo_dc0_waveforms.html

来自「用来实现VGA发生时序」· HTML 代码 · 共 17 行

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17 行

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<title>Sample Waveforms for lpm_fifo_dc0.v </title>
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<h2><CENTER>Sample behavioral waveforms for design file lpm_fifo_dc0.v </CENTER></h2>
<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.v. The design lpm_fifo_dc0.v has a depth of 16 words of 12 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions . </P>
<CENTER><img src=lpm_fifo_dc0_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
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lpm_fifo_dc0_waveforms.html - 源码说明

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