top.tan.rpt

基于FPGA的多波形发生器（编程环境QuartusII6.0）

+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                      ; From                                               ; To                                                                                                                                   ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; 0.912 ns                         ; altera_internal_jtag~TMSUTAP                       ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2]                                                                                          ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 21.597 ns                        ; tf_top:inst4|74374:inst4|15                        ; L[3]                                                                                                                                 ; clk2                         ;                              ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 14.142 ns                        ; n1                                                 ; out[2]                                                                                                                               ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 2.847 ns                         ; altera_internal_jtag                               ; SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A                                      ; None          ; 14.340 ns                        ; tf_top:inst4|74374:inst4|16                        ; L[6]                                                                                                                                 ; clk2                         ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A                                      ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                           ; altera_reserved_tdo                                                                                                                  ;                              ;                              ; 0            ;
; Clock Setup: 'clk2'                         ; N/A                                      ; None          ; 27.39 MHz ( period = 36.506 ns ) ; tf_top:inst4|conter8:inst|74390:inst|32            ; tf_top:inst4|74374:inst4|19                                                                                                          ; clk2                         ; clk2                         ; 0            ;
; Clock Setup: 'clk'                          ; N/A                                      ; None          ; 56.92 MHz ( period = 17.570 ns ) ; tf_top:inst4|conter8:inst|74390:inst|33            ; tf_top:inst4|conter8:inst|74390:inst|31                                                                                              ; clk                          ; clk                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 91.74 MHz ( period = 10.900 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                    ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Hold: 'clk2'                          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; tf_top:inst4|conter8:inst|74390:inst|33            ; tf_top:inst4|conter8:inst|74390:inst|33                                                                                              ; clk2                         ; clk2                         ; 10           ;
; Clock Hold: 'clk'                           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; tf_top:inst4|conter8:inst|74390:inst|33            ; tf_top:inst4|conter8:inst|74390:inst|33                                                                                              ; clk                          ; clk                          ; 8            ;
; Total number of failed paths                ;                                          ;               ;                                  ;                                                    ;                                                                                                                                      ;                              ;                              ; 18           ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                            ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; clk2                         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; clk                          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                           ; To                                                                                                                                                                                    ; From Clock                   ; To Clock                     ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 91.74 MHz ( period = 10.900 ns )                    ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2]                                                                                                                             ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                                                                     ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; None                    ;
; N/A                                     ; 95.80 MHz ( period = 10.438 ns )                    ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[1]                                                                                                                             ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                                                                     ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; None                    ;
; N/A                                     ; 97.71 MHz ( period = 10.234 ns )                    ; SJCRT:inst1|data_rom2:u1|altsyncram:altsyncram_component|altsyncram_mls:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                                                                     ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; None                    ;
; N/A                                     ; 98.97 MHz ( period = 10.104 ns )                    ; sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[0]                                                                                        ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                                                                     ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; None                    ;
; N/A                                     ; 100.46 MHz ( period = 9.954 ns )                    ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[2]                                                                                                                             ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                                                                     ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; None                    ;