top.hif

基于FPGA的多波形发生器（编程环境QuartusII6.0）

Version 4.1 Build 181 06/29/2004 SJ Full Version
31
OFF
OFF
OFF
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# entity
MUX41A
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
MUX41A.vhd
1182222148
4
# storage
db|top.(1).cnf
db|top.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
SINCRT
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
SINCRT.vhd
1182175418
4
# storage
db|top.(2).cnf
db|top.(2).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
data_rom1
# architecture
A:SYN
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
data_rom1.vhd
1182227422
4
# storage
db|top.(3).cnf
db|top.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|top.(4).cnf
db|top.(4).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
6
PARAMETER_DEC
USR
NUMWORDS_A
64
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
sin.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_q8s
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
c:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
c:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
c:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
c:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
c:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
c:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
c:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
c:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
altsyncram_q8s
# case_insensitive
# source_file
db|altsyncram_q8s.tdf
1182237356
6
# storage
db|top.(5).cnf
db|top.(5).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# end
# entity
altsyncram_gv92
# case_insensitive
# source_file
db|altsyncram_gv92.tdf
1182237356
6
# storage
db|top.(6).cnf
db|top.(6).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
clock0
clock1
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
sin.mif
1182223346
}
# end
# entity
sld_mod_ram_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
4
# storage
db|top.(7).cnf
db|top.(7).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
sld_node_info
1601024
PARAMETER_DEC
DEF
sld_ip_version
0
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
8
PARAMETER_UNKNOWN
USR
numwords
64
PARAMETER_UNKNOWN
USR
widthad
6
PARAMETER_UNKNOWN
USR
shift_count_bits
4
PARAMETER_UNKNOWN
USR
cvalue
00000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1919905073
PARAMETER_UNKNOWN
USR
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|sld_rom_sr.vhd
1088009284
4
# storage
db|top.(8).cnf
db|top.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
80
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|sld_mod_ram_rom.vhd
1088009288
}
# end
# entity
SJCRT
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
SJCRT.vhd
1182177364
4
# storage
db|top.(9).cnf
db|top.(9).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
data_rom2
# architecture
A:SYN
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
data_rom2.vhd
1182227534
4
# storage
db|top.(10).cnf
db|top.(10).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altsyncram.tdf
1088009418
6
# storage
db|top.(11).cnf
db|top.(11).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
6
PARAMETER_DEC
USR
NUMWORDS_A
64
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
sanjiao.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_mls
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|stratix_ram_block.inc
1081479498
c:|altera|quartus41|libraries|megafunctions|lpm_mux.inc
1081478758
c:|altera|quartus41|libraries|megafunctions|lpm_decode.inc
1081478592
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
c:|altera|quartus41|libraries|megafunctions|altsyncram.inc
1081477654
c:|altera|quartus41|libraries|megafunctions|a_rdenreg.inc
1081476578
c:|altera|quartus41|libraries|megafunctions|altrom.inc
1081477590
c:|altera|quartus41|libraries|megafunctions|altram.inc
1081477560
c:|altera|quartus41|libraries|megafunctions|altdpram.inc
1081477328
c:|altera|quartus41|libraries|megafunctions|altqpram.inc
1081477546
}
# end
# entity
altsyncram_mls
# case_insensitive
# source_file
db|altsyncram_mls.tdf
1182237358
6
# storage
db|top.(12).cnf
db|top.(12).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# end