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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "18 " "Warning: Found 18 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "tf_top:inst4\|conter8:inst\|inst2 " "Info: Detected gated clock tf_top:inst4\|conter8:inst\|inst2 as buffer" { } { { "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" { { 56 152 216 104 "inst2" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|inst2" } } } } } 0} { "Info" "ITAN_GATED_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|20 " "Info: Detected gated clock tf_top:inst4\|conter8:inst\|74390:inst\|20 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|20" } } } } } 0} { "Info" "ITAN_GATED_CLK" "tf_top:inst4\|conter8:inst\|inst1~24 " "Info: Detected gated clock tf_top:inst4\|conter8:inst\|inst1~24 as buffer" { } { { "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" { { 80 696 760 160 "inst1" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|inst1~24" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16 " "Info: Detected ripple clock tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|15 " "Info: Detected ripple clock tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|15 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|15" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|13 " "Info: Detected ripple clock tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|13 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|13" } } } } } 0} { "Info" "ITAN_GATED_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|29 " "Info: Detected gated clock tf_top:inst4\|conter8:inst\|74390:inst\|29 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|29" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|5 " "Info: Detected ripple clock tf_top:inst4\|conter8:inst\|74390:inst\|5 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 200 520 584 280 "5" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|5" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|6 " "Info: Detected ripple clock tf_top:inst4\|conter8:inst\|74390:inst\|6 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|6" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|7 " "Info: Detected ripple clock tf_top:inst4\|conter8:inst\|74390:inst\|7 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|7" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|3 " "Info: Detected ripple clock tf_top:inst4\|conter8:inst\|74390:inst\|3 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|3" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|33 " "Info: Detected ripple clock tf_top:inst4\|conter8:inst\|74390:inst\|33 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|33" } } } } } 0} { "Info" "ITAN_GATED_CLK" "tf_top:inst4\|tf_ctro:inst1\|inst8~98 " "Info: Detected gated clock tf_top:inst4\|tf_ctro:inst1\|inst8~98 as buffer" { } { { "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" { { 24 592 656 72 "inst8" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|tf_ctro:inst1\|inst8~98" } } } } } 0} { "Info" "ITAN_GATED_CLK" "tf_top:inst4\|tf_ctro:inst1\|74154:inst\|23~14 " "Info: Detected gated clock tf_top:inst4\|tf_ctro:inst1\|74154:inst\|23~14 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74154.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74154.bdf" { { 1048 720 784 1152 "23" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|tf_ctro:inst1\|74154:inst\|23~14" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|14 " "Info: Detected ripple clock tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|14 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|14" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|34 " "Info: Detected ripple clock tf_top:inst4\|conter8:inst\|74390:inst\|34 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|34" } } } } } 0} { "Info" "ITAN_GATED_CLK" "tf_top:inst4\|tf_ctro:inst1\|inst8~0 " "Info: Detected gated clock tf_top:inst4\|tf_ctro:inst1\|inst8~0 as buffer" { } { { "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" { { 24 592 656 72 "inst8" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|tf_ctro:inst1\|inst8~0" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tf_top:inst4\|conter8:inst\|74390:inst\|31 " "Info: Detected ripple clock tf_top:inst4\|conter8:inst\|74390:inst\|31 as buffer" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "tf_top:inst4\|conter8:inst\|74390:inst\|31" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[2\] register sld_hub:sld_hub_inst\|HUB_TDO~reg0 91.74 MHz 10.9 ns Internal " "Info: Clock altera_internal_jtag~TCKUTAP has Internal fmax of 91.74 MHz between source register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[2\] and destination register sld_hub:sld_hub_inst\|HUB_TDO~reg0 (period= 10.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.151 ns + Longest register register " "Info: + Longest register to register delay is 5.151 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[2\] 1 REG LC_X18_Y6_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y6_N7; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[2\]'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.568 ns) + CELL(0.292 ns) 0.860 ns sld_hub:sld_hub_inst\|HUB_TDO~859 2 COMB LC_X18_Y6_N9 2 " "Info: 2: + IC(0.568 ns) + CELL(0.292 ns) = 0.860 ns; Loc. = LC_X18_Y6_N9; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~859'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.860 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] sld_hub:sld_hub_inst|HUB_TDO~859 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.442 ns) 2.846 ns sld_hub:sld_hub_inst\|HUB_TDO~860 3 COMB LC_X20_Y4_N2 1 " "Info: 3: + IC(1.544 ns) + CELL(0.442 ns) = 2.846 ns; Loc. = LC_X20_Y4_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~860'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.986 ns" { sld_hub:sld_hub_inst|HUB_TDO~859 sld_hub:sld_hub_inst|HUB_TDO~860 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.224 ns) + CELL(0.590 ns) 4.660 ns sld_hub:sld_hub_inst\|HUB_TDO~861 4 COMB LC_X20_Y5_N7 1 " "Info: 4: + IC(1.224 ns) + CELL(0.590 ns) = 4.660 ns; Loc. = LC_X20_Y5_N7; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~861'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.814 ns" { sld_hub:sld_hub_inst|HUB_TDO~860 sld_hub:sld_hub_inst|HUB_TDO~861 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 5.151 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 5 REG LC_X20_Y5_N8 0 " "Info: 5: + IC(0.182 ns) + CELL(0.309 ns) = 5.151 ns; Loc. = LC_X20_Y5_N8; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.491 ns" { sld_hub:sld_hub_inst|HUB_TDO~861 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.633 ns 31.70 % " "Info: Total cell delay = 1.633 ns ( 31.70 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.518 ns 68.30 % " "Info: Total interconnect delay = 3.518 ns ( 68.30 % )" { } { } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "5.151 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] sld_hub:sld_hub_inst|HUB_TDO~859 sld_hub:sld_hub_inst|HUB_TDO~860 sld_hub:sld_hub_inst|HUB_TDO~861 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.038 ns - Smallest " "Info: - Smallest clock skew is -0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.854 ns + Shortest register " "Info: + Shortest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.854 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 264 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 264; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.143 ns) + CELL(0.711 ns) 4.854 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 2 REG LC_X20_Y5_N8 0 " "Info: 2: + IC(4.143 ns) + CELL(0.711 ns) = 4.854 ns; Loc. = LC_X20_Y5_N8; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.854 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.65 % " "Info: Total cell delay = 0.711 ns ( 14.65 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.143 ns 85.35 % " "Info: Total interconnect delay = 4.143 ns ( 85.35 % )" { } { } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.854 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.892 ns - Longest register " "Info: - Longest clock path from clock altera_internal_jtag~TCKUTAP to source register is 4.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 264 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 264; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.181 ns) + CELL(0.711 ns) 4.892 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[2\] 2 REG LC_X18_Y6_N7 3 " "Info: 2: + IC(4.181 ns) + CELL(0.711 ns) = 4.892 ns; Loc. = LC_X18_Y6_N7; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:3:IRF\|Q\[2\]'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.892 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.53 % " "Info: Total cell delay = 0.711 ns ( 14.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.181 ns 85.47 % " "Info: Total interconnect delay = 4.181 ns ( 85.47 % )" { } { } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.892 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] } "NODE_NAME" } } } } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.854 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.892 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } } } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "5.151 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] sld_hub:sld_hub_inst|HUB_TDO~859 sld_hub:sld_hub_inst|HUB_TDO~860 sld_hub:sld_hub_inst|HUB_TDO~861 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.854 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.892 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:3:IRF|Q[2] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk2 register tf_top:inst4\|conter8:inst\|74390:inst\|32 register tf_top:inst4\|74374:inst4\|19 27.39 MHz 36.506 ns Internal " "Info: Clock clk2 has Internal fmax of 27.39 MHz between source register tf_top:inst4\|conter8:inst\|74390:inst\|32 and destination register tf_top:inst4\|74374:inst4\|19 (period= 36.506 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.694 ns + Longest register register " "Info: + Longest register to register delay is 0.694 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tf_top:inst4\|conter8:inst\|74390:inst\|32 1 REG LC_X17_Y1_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y1_N9; Fanout = 3; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|32'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { tf_top:inst4|conter8:inst|74390:inst|32 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.115 ns) 0.694 ns tf_top:inst4\|74374:inst4\|19 2 REG LC_X17_Y1_N7 7 " "Info: 2: + IC(0.579 ns) + CELL(0.115 ns) = 0.694 ns; Loc. = LC_X17_Y1_N7; Fanout = 7; REG Node = 'tf_top:inst4\|74374:inst4\|19'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.694 ns" { tf_top:inst4|conter8:inst|74390:inst|32 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" { { 720 256 320 800 "19" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 16.57 % " "Info: Total cell delay = 0.115 ns ( 16.57 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 83.43 % " "Info: Total interconnect delay = 0.579 ns ( 83.43 % )" { } { } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.694 ns" { tf_top:inst4|conter8:inst|74390:inst|32 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-17.298 ns - Smallest " "Info: - Smallest clock skew is -17.298 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 destination 10.033 ns + Shortest register " "Info: + Shortest clock path from clock clk2 to destination register is 10.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk2 1 CLK PIN_124 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_124; Fanout = 1; CLK Node = 'clk2'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { clk2 } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { -32 848 1016 -16 "clk2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.806 ns) + CELL(0.935 ns) 4.216 ns tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16 2 REG LC_X12_Y10_N8 6 " "Info: 2: + IC(1.806 ns) + CELL(0.935 ns) = 4.216 ns; Loc. = LC_X12_Y10_N8; Fanout = 6; REG Node = 'tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.741 ns" { clk2 tf_top:inst4|tf_ctro:inst1|7493:inst13|16 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.114 ns) 5.160 ns tf_top:inst4\|tf_ctro:inst1\|inst8~98 3 COMB LC_X11_Y10_N5 2 " "Info: 3: + IC(0.830 ns) + CELL(0.114 ns) = 5.160 ns; Loc. = LC_X11_Y10_N5; Fanout = 2; COMB Node = 'tf_top:inst4\|tf_ctro:inst1\|inst8~98'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.944 ns" { tf_top:inst4|tf_ctro:inst1|7493:inst13|16 tf_top:inst4|tf_ctro:inst1|inst8~98 } "NODE_NAME" } } } { "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" { { 24 592 656 72 "inst8" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 5.456 ns tf_top:inst4\|tf_ctro:inst1\|inst8~0 4 COMB LC_X11_Y10_N6 9 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 5.456 ns; Loc. = LC_X11_Y10_N6; Fanout = 9; COMB Node = 'tf_top:inst4\|tf_ctro:inst1\|inst8~0'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.296 ns" { tf_top:inst4|tf_ctro:inst1|inst8~98 tf_top:inst4|tf_ctro:inst1|inst8~0 } "NODE_NAME" } } } { "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/tf_ctro.bdf" { { 24 592 656 72 "inst8" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.866 ns) + CELL(0.711 ns) 10.033 ns tf_top:inst4\|74374:inst4\|19 5 REG LC_X17_Y1_N7 7 " "Info: 5: + IC(3.866 ns) + CELL(0.711 ns) = 10.033 ns; Loc. = LC_X17_Y1_N7; Fanout = 7; REG Node = 'tf_top:inst4\|74374:inst4\|19'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.577 ns" { tf_top:inst4|tf_ctro:inst1|inst8~0 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" { { 720 256 320 800 "19" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.349 ns 33.38 % " "Info: Total cell delay = 3.349 ns ( 33.38 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.684 ns 66.62 % " "Info: Total interconnect delay = 6.684 ns ( 66.62 % )" { } { } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "10.033 ns" { clk2 tf_top:inst4|tf_ctro:inst1|7493:inst13|16 tf_top:inst4|tf_ctro:inst1|inst8~98 tf_top:inst4|tf_ctro:inst1|inst8~0 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 27.331 ns - Longest register " "Info: - Longest clock path from clock clk2 to source register is 27.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk2 1 CLK PIN_124 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_124; Fanout = 1; CLK Node = 'clk2'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { clk2 } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { -32 848 1016 -16 "clk2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.806 ns) + CELL(0.935 ns) 4.216 ns tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16 2 REG LC_X12_Y10_N8 6 " "Info: 2: + IC(1.806 ns) + CELL(0.935 ns) = 4.216 ns; Loc. = LC_X12_Y10_N8; Fanout = 6; REG Node = 'tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|16'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.741 ns" { clk2 tf_top:inst4|tf_ctro:inst1|7493:inst13|16 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.974 ns) + CELL(0.935 ns) 9.125 ns tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|13 3 REG LC_X11_Y10_N4 4 " "Info: 3: + IC(3.974 ns) + CELL(0.935 ns) = 9.125 ns; Loc. = LC_X11_Y10_N4; Fanout = 4; REG Node = 'tf_top:inst4\|tf_ctro:inst1\|7493:inst13\|13'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "4.909 ns" { tf_top:inst4|tf_ctro:inst1|7493:inst13|16 tf_top:inst4|tf_ctro:inst1|7493:inst13|13 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.576 ns) + CELL(0.292 ns) 9.993 ns tf_top:inst4\|conter8:inst\|inst2 4 COMB LC_X11_Y10_N3 1 " "Info: 4: + IC(0.576 ns) + CELL(0.292 ns) = 9.993 ns; Loc. = LC_X11_Y10_N3; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|inst2'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.868 ns" { tf_top:inst4|tf_ctro:inst1|7493:inst13|13 tf_top:inst4|conter8:inst|inst2 } "NODE_NAME" } } } { "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" { { 56 152 216 104 "inst2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.683 ns) + CELL(0.935 ns) 12.611 ns tf_top:inst4\|conter8:inst\|74390:inst\|7 5 REG LC_X12_Y2_N8 5 " "Info: 5: + IC(1.683 ns) + CELL(0.935 ns) = 12.611 ns; Loc. = LC_X12_Y2_N8; Fanout = 5; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|7'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.618 ns" { tf_top:inst4|conter8:inst|inst2 tf_top:inst4|conter8:inst|74390:inst|7 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.884 ns) + CELL(0.935 ns) 14.430 ns tf_top:inst4\|conter8:inst\|74390:inst\|3 6 REG LC_X11_Y2_N2 4 " "Info: 6: + IC(0.884 ns) + CELL(0.935 ns) = 14.430 ns; Loc. = LC_X11_Y2_N2; Fanout = 4; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|3'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.819 ns" { tf_top:inst4|conter8:inst|74390:inst|7 tf_top:inst4|conter8:inst|74390:inst|3 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.292 ns) 15.275 ns tf_top:inst4\|conter8:inst\|74390:inst\|20 7 COMB LC_X11_Y2_N5 1 " "Info: 7: + IC(0.553 ns) + CELL(0.292 ns) = 15.275 ns; Loc. = LC_X11_Y2_N5; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|20'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.845 ns" { tf_top:inst4|conter8:inst|74390:inst|3 tf_top:inst4|conter8:inst|74390:inst|20 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.935 ns) 16.666 ns tf_top:inst4\|conter8:inst\|74390:inst\|6 8 REG LC_X11_Y2_N8 5 " "Info: 8: + IC(0.456 ns) + CELL(0.935 ns) = 16.666 ns; Loc. = LC_X11_Y2_N8; Fanout = 5; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|6'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.391 ns" { tf_top:inst4|conter8:inst|74390:inst|20 tf_top:inst4|conter8:inst|74390:inst|6 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.935 ns) 18.377 ns tf_top:inst4\|conter8:inst\|74390:inst\|5 9 REG LC_X10_Y2_N6 4 " "Info: 9: + IC(0.776 ns) + CELL(0.935 ns) = 18.377 ns; Loc. = LC_X10_Y2_N6; Fanout = 4; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|5'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.711 ns" { tf_top:inst4|conter8:inst|74390:inst|6 tf_top:inst4|conter8:inst|74390:inst|5 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 200 520 584 280 "5" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.807 ns) + CELL(0.114 ns) 19.298 ns tf_top:inst4\|conter8:inst\|inst1~24 10 COMB LC_X11_Y2_N6 1 " "Info: 10: + IC(0.807 ns) + CELL(0.114 ns) = 19.298 ns; Loc. = LC_X11_Y2_N6; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|inst1~24'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.921 ns" { tf_top:inst4|conter8:inst|74390:inst|5 tf_top:inst4|conter8:inst|inst1~24 } "NODE_NAME" } } } { "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" { { 80 696 760 160 "inst1" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(0.935 ns) 21.830 ns tf_top:inst4\|conter8:inst\|74390:inst\|34 11 REG LC_X15_Y1_N4 4 " "Info: 11: + IC(1.597 ns) + CELL(0.935 ns) = 21.830 ns; Loc. = LC_X15_Y1_N4; Fanout = 4; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|34'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.532 ns" { tf_top:inst4|conter8:inst|inst1~24 tf_top:inst4|conter8:inst|74390:inst|34 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.935 ns) 23.571 ns tf_top:inst4\|conter8:inst\|74390:inst\|31 12 REG LC_X16_Y1_N4 3 " "Info: 12: + IC(0.806 ns) + CELL(0.935 ns) = 23.571 ns; Loc. = LC_X16_Y1_N4; Fanout = 3; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|31'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.741 ns" { tf_top:inst4|conter8:inst|74390:inst|34 tf_top:inst4|conter8:inst|74390:inst|31 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.561 ns) + CELL(0.292 ns) 24.424 ns tf_top:inst4\|conter8:inst\|74390:inst\|29 13 COMB LC_X16_Y1_N2 1 " "Info: 13: + IC(0.561 ns) + CELL(0.292 ns) = 24.424 ns; Loc. = LC_X16_Y1_N2; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|29'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.853 ns" { tf_top:inst4|conter8:inst|74390:inst|31 tf_top:inst4|conter8:inst|74390:inst|29 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.935 ns) 25.814 ns tf_top:inst4\|conter8:inst\|74390:inst\|33 14 REG LC_X16_Y1_N8 4 " "Info: 14: + IC(0.455 ns) + CELL(0.935 ns) = 25.814 ns; Loc. = LC_X16_Y1_N8; Fanout = 4; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|33'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.390 ns" { tf_top:inst4|conter8:inst|74390:inst|29 tf_top:inst4|conter8:inst|74390:inst|33 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.711 ns) 27.331 ns tf_top:inst4\|conter8:inst\|74390:inst\|32 15 REG LC_X17_Y1_N9 3 " "Info: 15: + IC(0.806 ns) + CELL(0.711 ns) = 27.331 ns; Loc. = LC_X17_Y1_N9; Fanout = 3; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|32'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.517 ns" { tf_top:inst4|conter8:inst|74390:inst|33 tf_top:inst4|conter8:inst|74390:inst|32 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.591 ns 42.41 % " "Info: Total cell delay = 11.591 ns ( 42.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.740 ns 57.59 % " "Info: Total interconnect delay = 15.740 ns ( 57.59 % )" { } { } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "27.331 ns" { clk2 tf_top:inst4|tf_ctro:inst1|7493:inst13|16 tf_top:inst4|tf_ctro:inst1|7493:inst13|13 tf_top:inst4|conter8:inst|inst2 tf_top:inst4|conter8:inst|74390:inst|7 tf_top:inst4|conter8:inst|74390:inst|3 tf_top:inst4|conter8:inst|74390:inst|20 tf_top:inst4|conter8:inst|74390:inst|6 tf_top:inst4|conter8:inst|74390:inst|5 tf_top:inst4|conter8:inst|inst1~24 tf_top:inst4|conter8:inst|74390:inst|34 tf_top:inst4|conter8:inst|74390:inst|31 tf_top:inst4|conter8:inst|74390:inst|29 tf_top:inst4|conter8:inst|74390:inst|33 tf_top:inst4|conter8:inst|74390:inst|32 } "NODE_NAME" } } } } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "10.033 ns" { clk2 tf_top:inst4|tf_ctro:inst1|7493:inst13|16 tf_top:inst4|tf_ctro:inst1|inst8~98 tf_top:inst4|tf_ctro:inst1|inst8~0 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "27.331 ns" { clk2 tf_top:inst4|tf_ctro:inst1|7493:inst13|16 tf_top:inst4|tf_ctro:inst1|7493:inst13|13 tf_top:inst4|conter8:inst|inst2 tf_top:inst4|conter8:inst|74390:inst|7 tf_top:inst4|conter8:inst|74390:inst|3 tf_top:inst4|conter8:inst|74390:inst|20 tf_top:inst4|conter8:inst|74390:inst|6 tf_top:inst4|conter8:inst|74390:inst|5 tf_top:inst4|conter8:inst|inst1~24 tf_top:inst4|conter8:inst|74390:inst|34 tf_top:inst4|conter8:inst|74390:inst|31 tf_top:inst4|conter8:inst|74390:inst|29 tf_top:inst4|conter8:inst|74390:inst|33 tf_top:inst4|conter8:inst|74390:inst|32 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" { { 720 256 320 800 "19" "" } } } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } } { "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" { { 720 256 320 800 "19" "" } } } } } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.694 ns" { tf_top:inst4|conter8:inst|74390:inst|32 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "10.033 ns" { clk2 tf_top:inst4|tf_ctro:inst1|7493:inst13|16 tf_top:inst4|tf_ctro:inst1|inst8~98 tf_top:inst4|tf_ctro:inst1|inst8~0 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "27.331 ns" { clk2 tf_top:inst4|tf_ctro:inst1|7493:inst13|16 tf_top:inst4|tf_ctro:inst1|7493:inst13|13 tf_top:inst4|conter8:inst|inst2 tf_top:inst4|conter8:inst|74390:inst|7 tf_top:inst4|conter8:inst|74390:inst|3 tf_top:inst4|conter8:inst|74390:inst|20 tf_top:inst4|conter8:inst|74390:inst|6 tf_top:inst4|conter8:inst|74390:inst|5 tf_top:inst4|conter8:inst|inst1~24 tf_top:inst4|conter8:inst|74390:inst|34 tf_top:inst4|conter8:inst|74390:inst|31 tf_top:inst4|conter8:inst|74390:inst|29 tf_top:inst4|conter8:inst|74390:inst|33 tf_top:inst4|conter8:inst|74390:inst|32 } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register tf_top:inst4\|conter8:inst\|74390:inst\|33 register tf_top:inst4\|conter8:inst\|74390:inst\|31 56.92 MHz 17.57 ns Internal " "Info: Clock clk has Internal fmax of 56.92 MHz between source register tf_top:inst4\|conter8:inst\|74390:inst\|33 and destination register tf_top:inst4\|conter8:inst\|74390:inst\|31 (period= 17.57 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.040 ns + Longest register register " "Info: + Longest register to register delay is 1.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tf_top:inst4\|conter8:inst\|74390:inst\|33 1 REG LC_X16_Y1_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y1_N8; Fanout = 4; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|33'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { tf_top:inst4|conter8:inst|74390:inst|33 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.478 ns) 1.040 ns tf_top:inst4\|conter8:inst\|74390:inst\|31 2 REG LC_X16_Y1_N4 3 " "Info: 2: + IC(0.562 ns) + CELL(0.478 ns) = 1.040 ns; Loc. = LC_X16_Y1_N4; Fanout = 3; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|31'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.040 ns" { tf_top:inst4|conter8:inst|74390:inst|33 tf_top:inst4|conter8:inst|74390:inst|31 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 45.96 % " "Info: Total cell delay = 0.478 ns ( 45.96 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.562 ns 54.04 % " "Info: Total interconnect delay = 0.562 ns ( 54.04 % )" { } { } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.040 ns" { tf_top:inst4|conter8:inst|74390:inst|33 tf_top:inst4|conter8:inst|74390:inst|31 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.484 ns - Smallest " "Info: - Smallest clock skew is -7.484 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.803 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 11.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 88 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 88; CLK Node = 'clk'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 264 -120 48 280 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.101 ns) + CELL(0.114 ns) 3.690 ns tf_top:inst4\|conter8:inst\|inst2 2 COMB LC_X11_Y10_N3 1 " "Info: 2: + IC(2.101 ns) + CELL(0.114 ns) = 3.690 ns; Loc. = LC_X11_Y10_N3; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|inst2'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.215 ns" { clk tf_top:inst4|conter8:inst|inst2 } "NODE_NAME" } } } { "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" { { 56 152 216 104 "inst2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.683 ns) + CELL(0.935 ns) 6.308 ns tf_top:inst4\|conter8:inst\|74390:inst\|7 3 REG LC_X12_Y2_N8 5 " "Info: 3: + IC(1.683 ns) + CELL(0.935 ns) = 6.308 ns; Loc. = LC_X12_Y2_N8; Fanout = 5; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|7'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.618 ns" { tf_top:inst4|conter8:inst|inst2 tf_top:inst4|conter8:inst|74390:inst|7 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.590 ns) 7.754 ns tf_top:inst4\|conter8:inst\|inst1~24 4 COMB LC_X11_Y2_N6 1 " "Info: 4: + IC(0.856 ns) + CELL(0.590 ns) = 7.754 ns; Loc. = LC_X11_Y2_N6; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|inst1~24'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.446 ns" { tf_top:inst4|conter8:inst|74390:inst|7 tf_top:inst4|conter8:inst|inst1~24 } "NODE_NAME" } } } { "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" { { 80 696 760 160 "inst1" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(0.935 ns) 10.286 ns tf_top:inst4\|conter8:inst\|74390:inst\|34 5 REG LC_X15_Y1_N4 4 " "Info: 5: + IC(1.597 ns) + CELL(0.935 ns) = 10.286 ns; Loc. = LC_X15_Y1_N4; Fanout = 4; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|34'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.532 ns" { tf_top:inst4|conter8:inst|inst1~24 tf_top:inst4|conter8:inst|74390:inst|34 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.711 ns) 11.803 ns tf_top:inst4\|conter8:inst\|74390:inst\|31 6 REG LC_X16_Y1_N4 3 " "Info: 6: + IC(0.806 ns) + CELL(0.711 ns) = 11.803 ns; Loc. = LC_X16_Y1_N4; Fanout = 3; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|31'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.517 ns" { tf_top:inst4|conter8:inst|74390:inst|34 tf_top:inst4|conter8:inst|74390:inst|31 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.760 ns 40.33 % " "Info: Total cell delay = 4.760 ns ( 40.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.043 ns 59.67 % " "Info: Total interconnect delay = 7.043 ns ( 59.67 % )" { } { } 0} } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "11.803 ns" { clk tf_top:inst4|conter8:inst|inst2 tf_top:inst4|conter8:inst|74390:inst|7 tf_top:inst4|conter8:inst|inst1~24 tf_top:inst4|conter8:inst|74390:inst|34 tf_top:inst4|conter8:inst|74390:inst|31 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.287 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 19.287 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 88 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 88; CLK Node = 'clk'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/EDA/multi-wave creator/top.bdf" "" "" { Schematic "D:/EDA/multi-wave creator/top.bdf" { { 264 -120 48 280 "clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.101 ns) + CELL(0.114 ns) 3.690 ns tf_top:inst4\|conter8:inst\|inst2 2 COMB LC_X11_Y10_N3 1 " "Info: 2: + IC(2.101 ns) + CELL(0.114 ns) = 3.690 ns; Loc. = LC_X11_Y10_N3; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|inst2'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.215 ns" { clk tf_top:inst4|conter8:inst|inst2 } "NODE_NAME" } } } { "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" "" "" { Schematic "h:/ѧϰ/eda/shiyan2/shi yan er/conter8.bdf" { { 56 152 216 104 "inst2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.683 ns) + CELL(0.935 ns) 6.308 ns tf_top:inst4\|conter8:inst\|74390:inst\|7 3 REG LC_X12_Y2_N8 5 " "Info: 3: + IC(1.683 ns) + CELL(0.935 ns) = 6.308 ns; Loc. = LC_X12_Y2_N8; Fanout = 5; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|7'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "2.618 ns" { tf_top:inst4|conter8:inst|inst2 tf_top:inst4|conter8:inst|74390:inst|7 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.884 ns) + CELL(0.935 ns) 8.127 ns tf_top:inst4\|conter8:inst\|74390:inst\|3 4 REG LC_X11_Y2_N2 4 " "Info: 4: + IC(0.884 ns) + CELL(0.935 ns) = 8.127 ns; Loc. = LC_X11_Y2_N2; Fanout = 4; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|3'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.819 ns" { tf_top:inst4|conter8:inst|74390:inst|7 tf_top:inst4|conter8:inst|74390:inst|3 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.292 ns) 8.972 ns tf_top:inst4\|conter8:inst\|74390:inst\|20 5 COMB LC_X11_Y2_N5 1 " "Info: 5: + IC(0.553 ns) + CELL(0.292 ns) = 8.972 ns; Loc. = LC_X11_Y2_N5; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|20'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.845 ns" { tf_top:inst4|conter8:inst|74390:inst|3 tf_top:inst4|conter8:inst|74390:inst|20 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.935 ns) 10.363 ns tf_top:inst4\|conter8:inst\|74390:inst\|6 6 REG LC_X11_Y2_N8 5 " "Info: 6: + IC(0.456 ns) + CELL(0.935 ns) = 10.363 ns; Loc. = LC_X11_Y2_N8; Fanout = 5; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|6'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.391 ns" { tf_top:inst4|conter8:inst|74390:inst|20 tf_top:inst4|conter8:inst|74390:inst|6 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.935 ns) 12.074 ns tf_top:inst4\|conter8:inst\|74390:inst\|5 7 REG LC_X10_Y2_N6 4 " "Info: 7: + IC(0.776 ns) + CELL(0.935 ns) = 12.074 ns; Loc. = LC_X10_Y2_N6; Fanout = 4; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|5'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "1.711 ns" { tf_top:inst4|conter8:inst|74390:inst|6 tf_top:inst4|conter8:inst|74390:inst|5 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 200 520 584 280 "5" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.807 ns) + CELL(0.114 ns) 12.995 ns tf_top:inst4\|conter8:inst\|inst1~24 8 COMB LC_X11_Y2_N6 1 " "Info: 8: + IC(0.807 ns) + CELL(0.114 ns) = 12.995 ns; Loc. = LC_X11_Y2_N6; Fanout = 1; COMB Node = 'tf_top:inst4\|conter8:inst\|inst1~24'" { } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/d⌨️ 快捷键说明
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