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基于FPGA的多波形发生器（编程环境QuartusII6.0）

|top
H[0] <= tf_top:inst4.H[0]
H[1] <= tf_top:inst4.H[1]
H[2] <= tf_top:inst4.H[2]
H[3] <= tf_top:inst4.H[3]
H[4] <= tf_top:inst4.H[4]
H[5] <= tf_top:inst4.H[5]
H[6] <= tf_top:inst4.H[6]
clk => tf_top:inst4.F_IN
clk => SINCRT:inst.CLK
clk => SJCRT:inst1.CLK
clk => JCCRT:inst2.CLK
clk2 => tf_top:inst4.CLK
L[0] <= tf_top:inst4.L[0]
L[1] <= tf_top:inst4.L[1]
L[2] <= tf_top:inst4.L[2]
L[3] <= tf_top:inst4.L[3]
L[4] <= tf_top:inst4.L[4]
L[5] <= tf_top:inst4.L[5]
L[6] <= tf_top:inst4.L[6]
out[0] <= MUX41A:inst3.DATAOUT[0]
out[1] <= MUX41A:inst3.DATAOUT[1]
out[2] <= MUX41A:inst3.DATAOUT[2]
out[3] <= MUX41A:inst3.DATAOUT[3]
out[4] <= MUX41A:inst3.DATAOUT[4]
out[5] <= MUX41A:inst3.DATAOUT[5]
out[6] <= MUX41A:inst3.DATAOUT[6]
out[7] <= MUX41A:inst3.DATAOUT[7]
n0 => MUX41A:inst3.s0
n1 => MUX41A:inst3.s1


|top|tf_top:inst4
COUT <= conter8:inst.cout
CLK => tf_ctro:inst1.clk
F_IN => conter8:inst.clk
H[0] <= 74248:inst3.OA
H[1] <= 74248:inst3.OB
H[2] <= 74248:inst3.OC
H[3] <= 74248:inst3.OD
H[4] <= 74248:inst3.OE
H[5] <= 74248:inst3.OF
H[6] <= 74248:inst3.OG
L[0] <= 74248:inst2.OA
L[1] <= 74248:inst2.OB
L[2] <= 74248:inst2.OC
L[3] <= 74248:inst2.OD
L[4] <= 74248:inst2.OE
L[5] <= 74248:inst2.OF
L[6] <= 74248:inst2.OG


|top|tf_top:inst4|conter8:inst
cout <= inst4.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= 74390:inst.1QA
q[1] <= 74390:inst.1QB
q[2] <= 74390:inst.1QC
q[3] <= 74390:inst.1QD
q[4] <= 74390:inst.2QA
q[5] <= 74390:inst.2QB
q[6] <= 74390:inst.2QC
q[7] <= 74390:inst.2QD
clr => 74390:inst.2CLR
clr => 74390:inst.1CLR
enb => inst2.IN0
clk => inst2.IN1


|top|tf_top:inst4|conter8:inst|74390:inst
2QA <= 34.DB_MAX_OUTPUT_PORT_TYPE
2CLR => 25.IN0
2CLKA => 24.IN0
2QB <= 33.DB_MAX_OUTPUT_PORT_TYPE
2QD <= 31.DB_MAX_OUTPUT_PORT_TYPE
2QC <= 32.DB_MAX_OUTPUT_PORT_TYPE
2CLKB => 27.IN0
2CLKB => 29.IN1
1QD <= 3.DB_MAX_OUTPUT_PORT_TYPE
1CLR => 22.IN0
1QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
1QB <= 6.DB_MAX_OUTPUT_PORT_TYPE
1CLKB => 20.IN1
1CLKB => 17.IN0
1QA <= 7.DB_MAX_OUTPUT_PORT_TYPE
1CLKA => 23.IN0


|top|tf_top:inst4|tf_ctro:inst1
CNT_EN <= inst12.DB_MAX_OUTPUT_PORT_TYPE
clk => 7493:inst13.CLKA
LOCK <= inst8.DB_MAX_OUTPUT_PORT_TYPE
CLR <= inst10.DB_MAX_OUTPUT_PORT_TYPE


|top|tf_top:inst4|tf_ctro:inst1|7493:inst13
QD <= 13.DB_MAX_OUTPUT_PORT_TYPE
RO1 => 1.IN0
RO2 => 1.IN1
CLKB => 44.IN0
QC <= 14.DB_MAX_OUTPUT_PORT_TYPE
QB <= 15.DB_MAX_OUTPUT_PORT_TYPE
QA <= 16.DB_MAX_OUTPUT_PORT_TYPE
CLKA => 43.IN0


|top|tf_top:inst4|tf_ctro:inst1|74154:inst
O0N <= 32.DB_MAX_OUTPUT_PORT_TYPE
G1N => 45.IN0
G2N => 45.IN1
A => 43.IN0
B => 40.IN0
C => 36.IN0
D => 34.IN0
O1N <= 31.DB_MAX_OUTPUT_PORT_TYPE
O2N <= 30.DB_MAX_OUTPUT_PORT_TYPE
O3N <= 29.DB_MAX_OUTPUT_PORT_TYPE
O4N <= 28.DB_MAX_OUTPUT_PORT_TYPE
O5N <= 27.DB_MAX_OUTPUT_PORT_TYPE
O6N <= 26.DB_MAX_OUTPUT_PORT_TYPE
O7N <= 25.DB_MAX_OUTPUT_PORT_TYPE
O8N <= 24.DB_MAX_OUTPUT_PORT_TYPE
O9N <= 23.DB_MAX_OUTPUT_PORT_TYPE
O10N <= 22.DB_MAX_OUTPUT_PORT_TYPE
O11N <= 21.DB_MAX_OUTPUT_PORT_TYPE
O12N <= 20.DB_MAX_OUTPUT_PORT_TYPE
O13N <= 19.DB_MAX_OUTPUT_PORT_TYPE
O14N <= 18.DB_MAX_OUTPUT_PORT_TYPE
O15N <= 17.DB_MAX_OUTPUT_PORT_TYPE


|top|tf_top:inst4|74248:inst3
OG <= 88.DB_MAX_OUTPUT_PORT_TYPE
B => 54.IN0
B => 57.IN1
A => 54.IN1
A => 56.IN1
RBIN => 54.IN2
RBIN => 54.IN3
C => 54.IN4
C => 58.IN1
D => 54.IN5
D => 62.IN0
BIN => 55.IN0
LTN => 60.IN1
LTN => 61.IN1
LTN => 64.IN1
LTN => 59.IN1
OF <= 89.DB_MAX_OUTPUT_PORT_TYPE
OE <= 90.DB_MAX_OUTPUT_PORT_TYPE
RBON <= 87.DB_MAX_OUTPUT_PORT_TYPE
OD <= 91.DB_MAX_OUTPUT_PORT_TYPE
OC <= 92.DB_MAX_OUTPUT_PORT_TYPE
OB <= 93.DB_MAX_OUTPUT_PORT_TYPE
OA <= 94.DB_MAX_OUTPUT_PORT_TYPE


|top|tf_top:inst4|74374:inst4
Q8 <= 47.DB_MAX_OUTPUT_PORT_TYPE
CLK => 20.CLK
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
D8 => 20.DATAIN
OEN => 2.IN0
Q7 <= 46.DB_MAX_OUTPUT_PORT_TYPE
D7 => 19.DATAIN
Q6 <= 45.DB_MAX_OUTPUT_PORT_TYPE
D6 => 18.DATAIN
Q5 <= 44.DB_MAX_OUTPUT_PORT_TYPE
D5 => 17.DATAIN
Q4 <= 43.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q3 <= 42.DB_MAX_OUTPUT_PORT_TYPE
D3 => 15.DATAIN
Q2 <= 41.DB_MAX_OUTPUT_PORT_TYPE
D2 => 14.DATAIN
Q1 <= 40.DB_MAX_OUTPUT_PORT_TYPE
D1 => 13.DATAIN


|top|tf_top:inst4|74248:inst2
OG <= 88.DB_MAX_OUTPUT_PORT_TYPE
B => 54.IN0
B => 57.IN1
A => 54.IN1
A => 56.IN1
RBIN => 54.IN2
RBIN => 54.IN3
C => 54.IN4
C => 58.IN1
D => 54.IN5
D => 62.IN0
BIN => 55.IN0
LTN => 60.IN1
LTN => 61.IN1
LTN => 64.IN1
LTN => 59.IN1
OF <= 89.DB_MAX_OUTPUT_PORT_TYPE
OE <= 90.DB_MAX_OUTPUT_PORT_TYPE
RBON <= 87.DB_MAX_OUTPUT_PORT_TYPE
OD <= 91.DB_MAX_OUTPUT_PORT_TYPE
OC <= 92.DB_MAX_OUTPUT_PORT_TYPE
OB <= 93.DB_MAX_OUTPUT_PORT_TYPE
OA <= 94.DB_MAX_OUTPUT_PORT_TYPE


|top|MUX41A:inst3
s0 => Mux~0.IN3
s0 => Mux~1.IN4
s0 => Mux~2.IN3
s0 => Mux~3.IN4
s0 => Mux~4.IN3
s0 => Mux~5.IN3
s0 => Mux~6.IN3
s0 => Mux~7.IN3
s0 => Mux~8.IN3
s0 => Mux~9.IN3
s1 => Mux~0.IN4
s1 => Mux~1.IN5
s1 => Mux~2.IN4
s1 => Mux~3.IN5
s1 => Mux~4.IN4
s1 => Mux~5.IN4
s1 => Mux~6.IN4
s1 => Mux~7.IN4
s1 => Mux~8.IN4
s1 => Mux~9.IN4
A[0] => Mux~9.IN0
A[1] => Mux~8.IN0
A[2] => Mux~7.IN0
A[3] => Mux~6.IN0
A[4] => Mux~5.IN0
A[5] => Mux~4.IN0
A[6] => Mux~2.IN0
A[7] => Mux~0.IN0
B[0] => Mux~9.IN1
B[1] => Mux~8.IN1
B[2] => Mux~7.IN1
B[3] => Mux~6.IN1
B[4] => Mux~5.IN1
B[5] => Mux~4.IN1
B[6] => Mux~2.IN1
B[7] => Mux~0.IN1
C[0] => Mux~9.IN2
C[1] => Mux~8.IN2
C[2] => Mux~7.IN2
C[3] => Mux~6.IN2
C[4] => Mux~5.IN2
C[5] => Mux~4.IN2
C[6] => Mux~2.IN2
C[7] => Mux~0.IN2
DATAOUT[0] <= DATAOUT[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[1] <= DATAOUT[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[2] <= DATAOUT[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[3] <= DATAOUT[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[4] <= DATAOUT[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[5] <= DATAOUT[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[6] <= DATAOUT[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
DATAOUT[7] <= DATAOUT[7]$latch.DB_MAX_OUTPUT_PORT_TYPE


|top|SINCRT:inst
CLK => Q1[4].CLK
CLK => Q1[3].CLK
CLK => Q1[2].CLK
CLK => Q1[1].CLK
CLK => Q1[0].CLK
CLK => data_rom1:u1.inclock
CLK => Q1[5].CLK
DOUT[0] <= data_rom1:u1.q[0]
DOUT[1] <= data_rom1:u1.q[1]
DOUT[2] <= data_rom1:u1.q[2]
DOUT[3] <= data_rom1:u1.q[3]
DOUT[4] <= data_rom1:u1.q[4]
DOUT[5] <= data_rom1:u1.q[5]
DOUT[6] <= data_rom1:u1.q[6]
DOUT[7] <= data_rom1:u1.q[7]


|top|SINCRT:inst|data_rom1:u1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|top|SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_q8s:auto_generated.address_a[0]
address_a[1] => altsyncram_q8s:auto_generated.address_a[1]
address_a[2] => altsyncram_q8s:auto_generated.address_a[2]
address_a[3] => altsyncram_q8s:auto_generated.address_a[3]
address_a[4] => altsyncram_q8s:auto_generated.address_a[4]
address_a[5] => altsyncram_q8s:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_q8s:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_q8s:auto_generated.q_a[0]
q_a[1] <= altsyncram_q8s:auto_generated.q_a[1]
q_a[2] <= altsyncram_q8s:auto_generated.q_a[2]
q_a[3] <= altsyncram_q8s:auto_generated.q_a[3]
q_a[4] <= altsyncram_q8s:auto_generated.q_a[4]
q_a[5] <= altsyncram_q8s:auto_generated.q_a[5]
q_a[6] <= altsyncram_q8s:auto_generated.q_a[6]
q_a[7] <= altsyncram_q8s:auto_generated.q_a[7]
q_b[0] <= <UNC>


|top|SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated
address_a[0] => altsyncram_gv92:altsyncram1.address_a[0]
address_a[1] => altsyncram_gv92:altsyncram1.address_a[1]
address_a[2] => altsyncram_gv92:altsyncram1.address_a[2]
address_a[3] => altsyncram_gv92:altsyncram1.address_a[3]
address_a[4] => altsyncram_gv92:altsyncram1.address_a[4]
address_a[5] => altsyncram_gv92:altsyncram1.address_a[5]
clock0 => altsyncram_gv92:altsyncram1.clock0
q_a[0] <= altsyncram_gv92:altsyncram1.q_a[0]
q_a[1] <= altsyncram_gv92:altsyncram1.q_a[1]
q_a[2] <= altsyncram_gv92:altsyncram1.q_a[2]
q_a[3] <= altsyncram_gv92:altsyncram1.q_a[3]
q_a[4] <= altsyncram_gv92:altsyncram1.q_a[4]
q_a[5] <= altsyncram_gv92:altsyncram1.q_a[5]
q_a[6] <= altsyncram_gv92:altsyncram1.q_a[6]
q_a[7] <= altsyncram_gv92:altsyncram1.q_a[7]


|top|SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|altsyncram_gv92:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3