top.fit.qmsg

基于FPGA的多波形发生器（编程环境QuartusII6.0）

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "1 " "Info: Fitter placement preparation operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.721 ns register register " "Info: Estimated most critical path is register to register delay of 0.721 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tf_top:inst4\|conter8:inst\|74390:inst\|32 1 REG LAB_X17_Y1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y1; Fanout = 3; REG Node = 'tf_top:inst4\|conter8:inst\|74390:inst\|32'" {  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { tf_top:inst4|conter8:inst|74390:inst|32 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(0.115 ns) 0.721 ns tf_top:inst4\|74374:inst4\|19 2 REG LAB_X17_Y1 7 " "Info: 2: + IC(0.606 ns) + CELL(0.115 ns) = 0.721 ns; Loc. = LAB_X17_Y1; Fanout = 7; REG Node = 'tf_top:inst4\|74374:inst4\|19'" {  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.721 ns" { tf_top:inst4|conter8:inst|74390:inst|32 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" "" "" { Schematic "c:/altera/quartus41/libraries/others/maxplus2/74374.bdf" { { 720 256 320 800 "19" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 15.95 % " "Info: Total cell delay = 0.115 ns ( 15.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.606 ns 84.05 % " "Info: Total interconnect delay = 0.606 ns ( 84.05 % )" {  } {  } 0}  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "0.721 ns" { tf_top:inst4|conter8:inst|74390:inst|32 tf_top:inst4|74374:inst4|19 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Info: Estimated interconnect usage is 6% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "1 " "Info: Fitter placement operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] " "Info: Port clear -- assigned as a global for destination node SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] -- routed using non-global resources" {  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\]" } } } } { "c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] " "Info: Port clear -- assigned as a global for destination node SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] -- routed using non-global resources" {  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\]" } } } } { "c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] " "Info: Port clear -- assigned as a global for destination node SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] -- routed using non-global resources" {  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\]" } } } } { "c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] " "Info: Port clear -- assigned as a global for destination node SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] -- routed using non-global resources" {  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SINCRT:inst\|data_rom1:u1\|altsyncram:altsyncram_component\|altsyncram_q8s:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\]" } } } } { "c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 624 -1 0 } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { SINCRT:inst|data_rom1:u1|altsyncram:altsyncram_component|altsyncram_q8s:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } }  } 0}  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]" } } } } { "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0}  } { { "D:/EDA/multi-wave creator/db/top_cmp.qrpt" "" "" { Report "D:/EDA/multi-wave creator/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/EDA/multi-wave creator/db/top.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/EDA/multi-wave creator/top.fld" "" "" { Floorplan "D:/EDA/multi-wave creator/top.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 19 17:25:41 2007 " "Info: Processing ended: Tue Jun 19 17:25:41 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}